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IEEE Transactions on Magnetics

A 1-GHz-clock Josephson microcomputer system

S. Yano, Y. Hatano, H. Mori, Hirotaka Yamada, K. Nakahara, Mutsuo Hirano, Ushio KAWABE

Published Mar 1, 1991• 16 citations
Publisher

Abstract

A 1-GHz-clock Josephson microcomputer system was developed to demonstrate the possibility of a high-speed superconducting computer system. It consists of a 4-b data processor chip and a 1-kb RAM chip. For the fabrication of these Josephson integrated circuits, a cross-shaped Nb-AlO/sub x/-Nb Josephson junction process was developed in order to realize small junction size and improve critical current uniformity, and has made fabrication of LSIs with several thousand gates possible. A latchup-free DC flip-flop is an important element in the high-speed Josephson logic and memory circuits, having been applied to an all-DC-powered Josephson RAM with asynchronous access capability. A low-inductance chip-to-chip carrier is an architectural and design concept for the Josephson computer's 1-GHz-clock operation, suppressing the crosstalk between the AC power and the output signals. Each chip is 7 mm square and is fabricated using a 2.5- mu m-rule Nb-AlO/sub x/-Nb junction process. The chips are connected on a superconducting carrier by solder bumps in a die size of 15 mm by 25 mm. The system is constructed from 8123 Josephson interferometer devices and is operable in a 1-ns cycle with 50-mW power dissipation.

DOI
10.1109/20.133750

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A 1-GHz-clock Josephson microcomputer system was developed to demonstrate the possibility of a high-speed superconducting computer system. It consists of a 4-b data processor chip and a 1-kb RAM chip. For the fabrication of these Josephson integrated circuits, a cross-shaped Nb-AlO/sub x/-Nb Josephson junction process was developed in order to realize small junction size and improve critical current uniformity, and has made fabrication of LSIs with several thousand gates possible. A latchup-free DC flip-flop is an important element in the high-speed Josephson logic and memory circuits, having been applied to an all-DC-powered Josephson RAM with asynchronous access capability. A low-inductance chip-to-chip carrier is an architectural and design concept for the Josephson computer's 1-GHz-clock operation, suppressing the crosstalk between the AC power and the output signals. Each chip is 7 mm square and is fabricated using a 2.5- mu m-rule Nb-AlO/sub x/-Nb junction process. The chips are connected on a superconducting carrier by solder bumps in a die size of 15 mm by 25 mm. The system is constructed from 8123 Josephson interferometer devices and is operable in a 1-ns cycle with 50-mW power dissipation.
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20 kA/cm2{\hbox{kA/cm}}^{2}kA/cm2 Process Development for Superconducting Integrated Circuits With 80 GHz Clock Frequency
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