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IEEE Transactions on Magnetics

A 4K Josephson memory

Hideo Suzuki, Norio Fujimaki, Hirotaka Tamura, T. Imamura, S. Hasuo

Published Mar 1, 1989• 51 citations
Publisher

Abstract

The authors describe the design and experimental performance of a 4 K*1-bit Josephson (RAM). For high-speed memory operation, the authors have developed a compact AND gate for the decoder, a high-voltage driver gate, and a capacitively coupled single-flux quantum memory cell. The 4 K memory was designed using these gates and cell and was fabricated with Nb/AlO/sub x//Nb junctions. The minimum access time was 590 ps, and the total power dissipation was 19 mW.>

DOI
10.1109/20.92404

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IEEE Transactions on Applied Superconductivity•Apr 22, 2014•22 citations
The authors describe the design and experimental performance of a 4 K*1-bit Josephson (RAM). For high-speed memory operation, the authors have developed a compact AND gate for the decoder, a high-voltage driver gate, and a capacitively coupled single-flux quantum memory cell. The 4 K memory was designed using these gates and cell and was fabricated with Nb/AlO/sub x//Nb junctions. The minimum access time was 590 ps, and the total power dissipation was 19 mW.>
An experimental memory model for investigating the feasibility of a 16K RAM memory with Josephson junctions was fabricated and tested. There are nearly 4500 Josephson junctions in the design which includes array, line drivers, and address decoders. Storage element is a single flux-quantum (SFQ) cell arranged in a 2K array. Drivers and decoders are based on the principle of current steering in superconducting loops, which is a medium speed but low power approach. The measured read-access time of the model is approximately 10 ns. Power dissipation of the unselected chip is zero, whereas for a read/write cycle time of 30 ns, it amounts to about 10 /spl mu/W. Results indicate that a 16K chip is feasible electrically. The estimated access time and power dissipation are 15 ns and 40 /spl nu/W, respectively.
The address decoders, address line drivers, and sense circuits of the fully decoded memory consist of resistor-coupled Josephson logic circuits to realize fast access. The memory cell is constructed from two three-junction symmetric SQUID (superconducting quantum interface device) gates, and a four-flux-quanta storage loop for enabling bipolar current drive. This memory configuration has intrinsic advantages in regard to magnetic flux trapping in address lines and a gate circuit latch-up problem over a DC-powered memory constructed from inductor coupled gates. Individual control and cell circuits were fabricated, using a lead-alloy process, and their operation was verified. A 570-ps read access time is estimated as the sum measured 280-ps decoding time, and calculated 130-ps address line current rising time, 110-ps sense time, and 50-ps signal propagation time. The 1-kb chip is designed to consume 9 mW without voltage regulators.>
A 2-kb nondestructive readout memory chip has been built using an Nb/AlO/sub x//Nb Josephson-junction process with a 2.5- mu m design rule. A bitmap of 56% functional cells among 1.5 K tested cells, a read access time of 200 ps, an average cycle time of 500 ps without the decoder, and a power dissipation of 1.6 mW including peripheral circuits have been obtained. The decoding time is estimated to be 540 ps. The circuits in this 5-mm by 5-mm, 24-pin chip includes 2 K memory cells, 6-b decoder and drivers, serial-to-parallel and parallel-to-serial converters, and circuits for design of testability or timing measurements. More than 14000 junctions are used on the chip.>
The design and experimental results for a novel type of Josephson memory cell are presented. The cell has a simpler construction than the conventional Henkels-type, using a one-junction SQUID (superconducting quantum interference device) capacitively coupled to a single junction. Binary data are stored as single flux quanta and are destructively read out by sensing a pulse caused by a vortex-mode transition. Computer simulations suggest that the read operation could be performed with a bias margin for the sense junction of +or-28% and that the rise time of the sense current in a 16-bit memory cell would be as fast as 30 ps, despite having to sense a vortex-mode transition. Results are presented for a memory cell fabricated with Nb-AlO/sub x/-Nb junctions.>
A new design concept for the Josephson-junction random access memory (RAM) has been developed. In contrast to previous RAMs based on single flux quantization (SFQ), in our system READ and WRITE operations employ ballistic transfer of SFQ pulses along bit lines (either Josephson transmission lines, or passive superconducting microstrip lines, or their combination). The basic memory cells are the single-junction SQUIDs, connected serially by the bit lines and inductively coupled to word lines. READ and WRITE operations are performed by sending SFQ pulses in appropriate directions along bit lines, and DC currents of appropriate polarity into word lines. This approach allows design of very dense memories with n/spl les/2 Josephson junctions per bit, memory cell area smaller than 80 /spl lambda//sup 2/ (where /spl lambda/ is the minimum feature size), and the critical parameter margin well above /spl plusmn/20%. In this paper we present the general structure of the RSFQ RAM, as well as design and results of testing of the basic memory cell and decoder circuitry using Hypres' 3.5-/spl mu/m, 1-kA/cm/sup 2/ Nb-trilayer technology.>
Superconductor electronics offers logic circuits for high-speed data processing and high-performance computing. The main barrier to practical application is the lack of high-speed and low-power memory. It is widely believed that the most reliable and functional bit cell for superconducting memory is the vortex transitional bit cell, which was successfully used by Nagasawa in a 4-kb memory. This paper reviews existing challenges in this type of Josephson memory devices and discusses engineering issues in implementing a model single flux quantum random access memory. We evaluate the contributions that various components of the memory system make to delay and power dissipation. The 256-bit memory provides an experimentally confirmed read access time of 190 ps. As a result, we found that delay and power dissipation are found largely in the address decoder, line drivers, bit-selection scheme, and the data readout circuitry. With these circuits being similar for various magnetic memory devices, our findings provide essential data for a comprehensive assessment of new concepts for bit cells, readout, and write in superconducting memories.