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IEEE Transactions on Applied Superconductivity

Rapid single flux quantum random access memory

Stanislav V. Polonsky, Alex F. Kirichenko, Vasili K. Semenov, K. K. Likharev

Published Jun 1, 1995• 45 citations
Publisher

Abstract

A new design concept for the Josephson-junction random access memory (RAM) has been developed. In contrast to previous RAMs based on single flux quantization (SFQ), in our system READ and WRITE operations employ ballistic transfer of SFQ pulses along bit lines (either Josephson transmission lines, or passive superconducting microstrip lines, or their combination). The basic memory cells are the single-junction SQUIDs, connected serially by the bit lines and inductively coupled to word lines. READ and WRITE operations are performed by sending SFQ pulses in appropriate directions along bit lines, and DC currents of appropriate polarity into word lines. This approach allows design of very dense memories with n/spl les/2 Josephson junctions per bit, memory cell area smaller than 80 /spl lambda//sup 2/ (where /spl lambda/ is the minimum feature size), and the critical parameter margin well above /spl plusmn/20%. In this paper we present the general structure of the RSFQ RAM, as well as design and results of testing of the basic memory cell and decoder circuitry using Hypres' 3.5-/spl mu/m, 1-kA/cm/sup 2/ Nb-trilayer technology.>

DOI
10.1109/77.403223

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Key digital circuits for signal processing with tens of gigahertz speed and a few microwatts power dissipation have been recently demonstrated using a simple, 2 /spl mu/m linewidth process. These are the fastest digital circuits reported to date. These circuits use novel rapid single flux quantum (RSFQ) technology that takes advantage of the fundamental properties of superconductivity. In this technology, data and clock are picosecond-long quantized voltage pulses corresponding to the transfer of single magnetic flux quanta, /spl Phisub 0/=h/2e=2 mVps. These SFQ pulses are regenerated at each gate and are processed by circuits comprised of overdamped Josephson junctions interconnected via microstrip inductances. The inherent internal memory of all RSFQ gates (primarily flip-flops), combined with high switching speed, makes serial, bit-pipelined circuit design advantageous. This paper presents experiments in RSFQ digital circuits, including an N/spl times/8b serial multiplier, and on-chip test systems based on RSFQ shift registers and on SFQ samplers. They enable test and study of RSFQ circuits at full GHz speed while communicating with semiconductor electronics at low speed.>

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A new design concept for the Josephson-junction random access memory (RAM) has been developed. In contrast to previous RAMs based on single flux quantization (SFQ), in our system READ and WRITE operations employ ballistic transfer of SFQ pulses along bit lines (either Josephson transmission lines, or passive superconducting microstrip lines, or their combination). The basic memory cells are the single-junction SQUIDs, connected serially by the bit lines and inductively coupled to word lines. READ and WRITE operations are performed by sending SFQ pulses in appropriate directions along bit lines, and DC currents of appropriate polarity into word lines. This approach allows design of very dense memories with n/spl les/2 Josephson junctions per bit, memory cell area smaller than 80 /spl lambda//sup 2/ (where /spl lambda/ is the minimum feature size), and the critical parameter margin well above /spl plusmn/20%. In this paper we present the general structure of the RSFQ RAM, as well as design and results of testing of the basic memory cell and decoder circuitry using Hypres' 3.5-/spl mu/m, 1-kA/cm/sup 2/ Nb-trilayer technology.>
We describe the design of a fast single-flux-quantum decoder which can be used, e.g., in fast RAMs, general-purpose microprocessors, and communication channel switches. The core of the circuit is a tree of the single-bit SFQ demultiplexer with toggle (rather than the reset-set) control. Three new RSFQ cells: the demultiplexer, D flip-flop with complementary outputs, and serial XOR with large parameter tolerances (dc bias margins of /spl plusmn/25%, /spl plusmn/26%, and /spl plusmn/27%, respectively) have been developed for the decoder project. We have designed the first 16-bit prototype of the decoder for 1-kA/cm/sup 2/ niobium-trilayer technology and tested it at low frequencies. The circuit was completely operable except for 3 (of 16) output SFQ/DC converters. Simulations show that the circuit should allow data rate in excess of 60 Gbit/s and channel switching time below 20 ps.>
An experimental memory model for investigating the feasibility of a 16K RAM memory with Josephson junctions was fabricated and tested. There are nearly 4500 Josephson junctions in the design which includes array, line drivers, and address decoders. Storage element is a single flux-quantum (SFQ) cell arranged in a 2K array. Drivers and decoders are based on the principle of current steering in superconducting loops, which is a medium speed but low power approach. The measured read-access time of the model is approximately 10 ns. Power dissipation of the unselected chip is zero, whereas for a read/write cycle time of 30 ns, it amounts to about 10 /spl mu/W. Results indicate that a 16K chip is feasible electrically. The estimated access time and power dissipation are 15 ns and 40 /spl nu/W, respectively.
We designed a superconducting random access memory (RAM) in which all component circuits can be operated with dc-bias currents. A dc-powered superconducting loop driver and a dc-powered sense circuit are effectively combined with single flux quantum (SFQ) circuits. We proposed a pipeline structure for the memory cell array composed of the dc-powered loop drivers, the dc-powered sense circuits, passive transmission lines (PTLs), and SFQ gates. This pipeline structure enables a clock operation of 10 GHz even in a large-scale RAM. An effective device structure for the RAM based on a planarized multi-layer device structure was proposed. A dc-power layer and two PTL layers were placed under the ground plane. This structure is indispensable to create the pipeline structure using PTLs. The large inductance formed in the power layer enables low power dissipation of the RAM. We found from the estimations that 10 GHz clock operation with extremely low power dissipation can be achieved even in a large-scale RAM of 1 Mbit.
Purpose The lack of reliable and scalable superconducting random access memory (RAM) cells is the main obstacle for full implementation of superconducting rapid single flux quantum(RSFQ) computers. This work points the methodology and the structures that shall be used in future implementation of RSFQ RAM. Design/methodology/approach A new design for RAM using two ferromagnetic strips in proximity to the superconductor in a RSFQ computer is presented (1). The concept of using a RAM RSFQ cell as a tuneable superconducting qubit is also explored. Findings Two basic architectures for superconducting RAM cells were developed with integration schemes in two dimensions. Research limitations/implications The proposed RAM cells as depicted in Figures 7 and 16 offer smaller size and greater 3 scalability in comparison to other suggested schemes (4), (3), (2), (5). Practical implications Currently, the main obstacle in implementation of RSQF computer is lack of reliable RAM cell. RSQF computer shall have potential to take a large fraction of classical supercomputers, as it consumes much less power. Social implications Computation power shall be cheaper when one uses RSQF computers for big data and computational centres. It is a matter of some time. Originality/value The publication presents the new design of superconducting RAM cell for use in RSQF computer. The numerical relaxation method is used to solve biharmonic Ginzburg–Landau equation. The analytic approach as a solution of a specified problem is given.
Abstract In this paper, a shift register (SR) memory based on rapid single flux quantum (RSFQ) logic for bit-parallel access is proposed. The memory cell changes from a row in the memory array to a column to increase the bit of data accessed per one clock cycle. The design of the 8 bit × 2 bit (8 × 2) memory is introduced. The memory consists of four parts: a SR memory array, an input buffer, an output buffer, and a controller, in which the controller is used to produce a control signal at a certain clock cycle specified by the address data. We have obtained the low speed test of the 8 × 2 memory fabricated by 6 kA cm −2 Nb process (SIMIT-Nb03), all bit-parallel access operations (write, read, clear and write, and read again) have been verified. We also simulated the 8 × 8 memory with data width expansion and obtained the maximum operating frequency of 34 GHz after the place and route with the SIMIT-Nb03 cell library. Based on the hierarchical storage, we have used the 8 × 8 memory as a basic block to construct large size of memory system, the access time and bandwidth have been evaluated. The bit-parallel memory shows higher bandwidth than bit-serial memory with the same capacity, especially for large capacity memory.
Key digital circuits for signal processing with tens of gigahertz speed and a few microwatts power dissipation have been recently demonstrated using a simple, 2 /spl mu/m linewidth process. These are the fastest digital circuits reported to date. These circuits use novel rapid single flux quantum (RSFQ) technology that takes advantage of the fundamental properties of superconductivity. In this technology, data and clock are picosecond-long quantized voltage pulses corresponding to the transfer of single magnetic flux quanta, /spl Phisub 0/=h/2e=2 mVps. These SFQ pulses are regenerated at each gate and are processed by circuits comprised of overdamped Josephson junctions interconnected via microstrip inductances. The inherent internal memory of all RSFQ gates (primarily flip-flops), combined with high switching speed, makes serial, bit-pipelined circuit design advantageous. This paper presents experiments in RSFQ digital circuits, including an N/spl times/8b serial multiplier, and on-chip test systems based on RSFQ shift registers and on SFQ samplers. They enable test and study of RSFQ circuits at full GHz speed while communicating with semiconductor electronics at low speed.>