Purpose The lack of reliable and scalable superconducting random access memory (RAM) cells is the main obstacle for full implementation of superconducting rapid single flux quantum(RSFQ) computers. This work points the methodology and the structures that shall be used in future implementation of RSFQ RAM. Design/methodology/approach A new design for RAM using two ferromagnetic strips in proximity to the superconductor in a RSFQ computer is presented (1). The concept of using a RAM RSFQ cell as a tuneable superconducting qubit is also explored. Findings Two basic architectures for superconducting RAM cells were developed with integration schemes in two dimensions. Research limitations/implications The proposed RAM cells as depicted in Figures 7 and 16 offer smaller size and greater 3 scalability in comparison to other suggested schemes (4), (3), (2), (5). Practical implications Currently, the main obstacle in implementation of RSQF computer is lack of reliable RAM cell. RSQF computer shall have potential to take a large fraction of classical supercomputers, as it consumes much less power. Social implications Computation power shall be cheaper when one uses RSQF computers for big data and computational centres. It is a matter of some time. Originality/value The publication presents the new design of superconducting RAM cell for use in RSQF computer. The numerical relaxation method is used to solve biharmonic Ginzburg–Landau equation. The analytic approach as a solution of a specified problem is given.
Purpose The lack of reliable and scalable superconducting random access memory (RAM) cells is the main obstacle for full implementation of superconducting rapid single flux quantum(RSFQ) computers. This work points the methodology and the structures that shall be used in future implementation of RSFQ RAM. Design/methodology/approach A new design for RAM using two ferromagnetic strips in proximity to the superconductor in a RSFQ computer is presented (1). The concept of using a RAM RSFQ cell as a tuneable superconducting qubit is also explored. Findings Two basic architectures for superconducting RAM cells were developed with integration schemes in two dimensions. Research limitations/implications The proposed RAM cells as depicted in Figures 7 and 16 offer smaller size and greater 3 scalability in comparison to other suggested schemes (4), (3), (2), (5). Practical implications Currently, the main obstacle in implementation of RSQF computer is lack of reliable RAM cell. RSQF computer shall have potential to take a large fraction of classical supercomputers, as it consumes much less power. Social implications Computation power shall be cheaper when one uses RSQF computers for big data and computational centres. It is a matter of some time. Originality/value The publication presents the new design of superconducting RAM cell for use in RSQF computer. The numerical relaxation method is used to solve biharmonic Ginzburg–Landau equation. The analytic approach as a solution of a specified problem is given.
A new design concept for the Josephson-junction random access memory (RAM) has been developed. In contrast to previous RAMs based on single flux quantization (SFQ), in our system READ and WRITE operations employ ballistic transfer of SFQ pulses along bit lines (either Josephson transmission lines, or passive superconducting microstrip lines, or their combination). The basic memory cells are the single-junction SQUIDs, connected serially by the bit lines and inductively coupled to word lines. READ and WRITE operations are performed by sending SFQ pulses in appropriate directions along bit lines, and DC currents of appropriate polarity into word lines. This approach allows design of very dense memories with n/spl les/2 Josephson junctions per bit, memory cell area smaller than 80 /spl lambda//sup 2/ (where /spl lambda/ is the minimum feature size), and the critical parameter margin well above /spl plusmn/20%. In this paper we present the general structure of the RSFQ RAM, as well as design and results of testing of the basic memory cell and decoder circuitry using Hypres' 3.5-/spl mu/m, 1-kA/cm/sup 2/ Nb-trilayer technology.>
Superconductor electronics offers logic circuits for high-speed data processing and high-performance computing. The main barrier to practical application is the lack of high-speed and low-power memory. It is widely believed that the most reliable and functional bit cell for superconducting memory is the vortex transitional bit cell, which was successfully used by Nagasawa in a 4-kb memory. This paper reviews existing challenges in this type of Josephson memory devices and discusses engineering issues in implementing a model single flux quantum random access memory. We evaluate the contributions that various components of the memory system make to delay and power dissipation. The 256-bit memory provides an experimentally confirmed read access time of 190 ps. As a result, we found that delay and power dissipation are found largely in the address decoder, line drivers, bit-selection scheme, and the data readout circuitry. With these circuits being similar for various magnetic memory devices, our findings provide essential data for a comprehensive assessment of new concepts for bit cells, readout, and write in superconducting memories.
ENGLISH ABSTRACT: Rapid Single Flux Quantum (RSFQ) cells are key in the design of complex and applicable RSFQ electronic circuits. These cells are low-level circuit elements that are used repeatedly to build larger, applicable RSFQ circuitry. Making these cells simple to layout and manufacture, but reliable for extensive use demands a careful development process for RSFQ cells. Cell functionality is verified through simulations, thereafter the cell is laid out in special software packages. Inductance of on-chip superconductor structures is extracted through careful modelling with numerical field solver software. A cell library has been developed by incorporating existing or published cells after further analysis and optimization, as well as developing new cells. Cells that have been adapted into the library include the Josephson transmission line (JTL), Splitter, Merger, D-Flip Flop (DFF), T-Flip Flop (TFF), NOT, AND, OR and XOR, DC-SFQ and SFQ-DC and PTL Driver and Receivers. New cells include NOR, NAND and XNOR. The cells were designed for the IPHT’s RSFQ1D 1kA/cmª and Hypres’ 4.5kA/cmª processes. The cells in the library have good bias current operating margins obtained through simulations (> ±26%). All cells have all the parameters listed in the thesis including extracted inductance values. In order to have a complete and verified RSFQ cell library, cells have been sent for fabrication at IPHT and Hypres facilities. These cells can now be tested on-chip, in the laboratory, to establish functionality and practical bias current margins. All test signal patterns and bias currents required for testing are defined to allow co-workers or collaborators to test the cells.
The lack of dense random-access memory is one of the main obstacles to the development of digital superconducting computers. It has been suggested that AVRAM cells, based on the storage of a single Abrikosov vortex-the smallest quantized object in superconductors-can enable drastic miniaturization to the nanometer scale. In this work, we present the numerical modeling of such cells using time-dependent Ginzburg-Landau equations. The cell represents a fluxonic quantum dot containing a small superconducting island, an asymmetric notch for the vortex entrance, a guiding track, and a vortex trap. We determine the optimal geometrical parameters for operation at zero magnetic field and the conditions for controllable vortex manipulation by short current pulses. We report ultrafast vortex motion with velocities more than an order of magnitude faster than those expected for macroscopic superconductors. This phenomenon is attributed to strong interactions with the edges of a mesoscopic island, combined with the nonlinear reduction of flux-flow viscosity due to the nonequilibrium effects in the track. Our results show that such cells can be scaled down to sizes comparable to the London penetration depth, ∼100 nm, and can enable ultrafast switching on the picosecond scale with ultralow energy per operation, ∼10-19 J.
We designed a superconducting random access memory (RAM) in which all component circuits can be operated with dc-bias currents. A dc-powered superconducting loop driver and a dc-powered sense circuit are effectively combined with single flux quantum (SFQ) circuits. We proposed a pipeline structure for the memory cell array composed of the dc-powered loop drivers, the dc-powered sense circuits, passive transmission lines (PTLs), and SFQ gates. This pipeline structure enables a clock operation of 10 GHz even in a large-scale RAM. An effective device structure for the RAM based on a planarized multi-layer device structure was proposed. A dc-power layer and two PTL layers were placed under the ground plane. This structure is indispensable to create the pipeline structure using PTLs. The large inductance formed in the power layer enables low power dissipation of the RAM. We found from the estimations that 10 GHz clock operation with extremely low power dissipation can be achieved even in a large-scale RAM of 1 Mbit.
In comparison to the widely-used CMOS circuits, superconducting Rapid Single Flux Quantum (RSFQ) circuits offer advantages such as fast operating frequency and low power consumption, making them a potential direction for development in the post-Moore era of digital circuits. However, designing RSFQ CPUs faces challenges, one of which is the need for a compact register file. This is because, under current RSFQ circuit process conditions, the memory module typically occupies a large chip area. This paper proposes a newly-designed Write-controllable Non-Destructive Read Out cell (WNDRO) that can limit the data writing pulse input to change the internal state of the cell. Based on the WNDRO, a compact RSFQ register file is designed that can realize random, non-destructive data reading. Additionally, a global write strategy is applied to omit the data write routing circuit and the reset control module, and the circuit design of the read and write control module is optimized. In comparison to general designs, the proposed compact register file design will save a large number of Josephson Junctions and effectively reduce the chip area. Additionally, this paper proposes several optimization logic designs for RSFQ CPU designers as a reference.