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IEEE Transactions on Circuits and Systems I Regular Papers

Design of a Compact Superconducting RSFQ Register File

Kuozhong Zhang, Zhimin Zhang, Guang-Ming Tang, Xiaochun Ye

Published Sep 18, 2023• 1 citation
Publisher

Abstract

In comparison to the widely-used CMOS circuits, superconducting Rapid Single Flux Quantum (RSFQ) circuits offer advantages such as fast operating frequency and low power consumption, making them a potential direction for development in the post-Moore era of digital circuits. However, designing RSFQ CPUs faces challenges, one of which is the need for a compact register file. This is because, under current RSFQ circuit process conditions, the memory module typically occupies a large chip area. This paper proposes a newly-designed Write-controllable Non-Destructive Read Out cell (WNDRO) that can limit the data writing pulse input to change the internal state of the cell. Based on the WNDRO, a compact RSFQ register file is designed that can realize random, non-destructive data reading. Additionally, a global write strategy is applied to omit the data write routing circuit and the reset control module, and the circuit design of the read and write control module is optimized. In comparison to general designs, the proposed compact register file design will save a large number of Josephson Junctions and effectively reduce the chip area. Additionally, this paper proposes several optimization logic designs for RSFQ CPU designers as a reference.

DOI
10.1109/tcsi.2023.3298768

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In comparison to the widely-used CMOS circuits, superconducting Rapid Single Flux Quantum (RSFQ) circuits offer advantages such as fast operating frequency and low power consumption, making them a potential direction for development in the post-Moore era of digital circuits. However, designing RSFQ CPUs faces challenges, one of which is the need for a compact register file. This is because, under current RSFQ circuit process conditions, the memory module typically occupies a large chip area. This paper proposes a newly-designed Write-controllable Non-Destructive Read Out cell (WNDRO) that can limit the data writing pulse input to change the internal state of the cell. Based on the WNDRO, a compact RSFQ register file is designed that can realize random, non-destructive data reading. Additionally, a global write strategy is applied to omit the data write routing circuit and the reset control module, and the circuit design of the read and write control module is optimized. In comparison to general designs, the proposed compact register file design will save a large number of Josephson Junctions and effectively reduce the chip area. Additionally, this paper proposes several optimization logic designs for RSFQ CPU designers as a reference.
Single Flux Quantum (SFQ) superconducting technology provides significant power and performance benefits in the era of diminishing CMOS scaling. Recent advances in design tools and fabrication facilities have brought SFQ based computing to the forefront. One challenge faced by SFQ technology is to have a compact and robust on-chip memory, which can be used for implementing register files and cache memory. While dense memories are being investigated through the development of three-terminal devices such as Nanocryotrons, in this work, we build on a novel memory cell built using traditional Josephson junctions (JJs). In particular, we design a high capacity register file, called HiPerRF, that builds on a High Capacity Destructive ReadOut (HC-DRO) cell in SFQ technology. HC-DRO design can store up to three fluxon pulses, thereby providing the equivalent of 2-bit storage in a single cell. However, these cells provide only destructive readout capability, namely each value can be read only once. However, CPU register file contents are read multiple times in any program, and hence a destructive readout complicates register file design. HiPerRF provides the non-destructive property using a loopback write mechanism, thereby preserving the higher density of HC-DRO cells without compromising the multi-read demands of a register file. HiPerRF reduces the JJ count of the register file design, after accounting for all the peripheral access circuitry costs, by 56.1% and reduces the static power by 46.2%. Furthermore, HiPerRF reduces the JJ count by 16.3% even when considering an entire in-order RISC-V CPU core.
Superconducting digital technology based on Rapid Single Flux Quantum logic (RSFQ) is a digital technology characterized by high speed, low power consumption and low operational temperatures. RSFQ is attractive for many applications and in particular for high frequency Digital Signal Processing (DSP) and for digital control of mK devices like superconducting qubits. Due to the 30 GHz clock speed, RSFQ DSP could be used to implement a Successive Interference Canceller for multi-user detection in a 3G wireless systems. The being developed DSP consists of a digital core, an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory and external semiconductor memory.The first part of this thesis is focusing on architecture and implementation of the hierarchical CMOS-RSFQ hybrid memory for the RSFQ DSP. The architecture ofthe RSFQ cache is optimized in order to reach the highest speed and reliable data communication with CMOS memory. Aspects of block synchronization betweenthe RSFQ cache and the RSFQ digital core are discussed and solved using a new developed RSFQ gate, C3. For design of different components of the DSP, a designapproach based on validated VHDL models is proposed and experimentally verified.The second part of this thesis is focusing on the design oflow-dissipative RSFQ circuits for interface to the superconducting qubits. Power dissipation ofRSFQ circuits is minimized. A low-temperature thermal model of resistively shunted Josephsonjunctions is developed and applied to optimize the shape of the shunt resistors in order to reduce their electron temperature. Depending on the available fabricationprocess the lowest noise temperature of RSFQ circuit can be in the range from 90 mK to 180 mK.
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
Abstract One of the main challenges for single flux quantum (SFQ) technology to successfully implement a microprocessor is to have a compact and robust on-chip memory that can be used for register files and cache memory. In this context, we designed high capacity destructive readout (HC-DRO) cells. The design is based on our insight that each cell can store more than one SFQ pulse with the same area footprint of a regular DRO cell. In our current design, we demonstrate a single HC-DRO cell that can store up to three SFQ pulses thereby enabling us to store the equivalent of two bits of memory in a single cell. We have designed a register file (RF) architecture for a microprocessor and used the HC-DRO cells to reduce the Josephson junction count required for its implementation. The RF architecture presented in this work can also be used for implementing cache memories. We also demonstrate the benefits of doubling the storage density with HC-DRO cells by designing a 2-bit branch predictor circuit block for a 5-stage pipeline microprocessor that dramatically improves the cycles per instruction metric of an SFQ based microprocessor. All the design details are presented in the paper by verifying the design concepts through JSIM simulations and Verilog simulations.
A new design concept for the Josephson-junction random access memory (RAM) has been developed. In contrast to previous RAMs based on single flux quantization (SFQ), in our system READ and WRITE operations employ ballistic transfer of SFQ pulses along bit lines (either Josephson transmission lines, or passive superconducting microstrip lines, or their combination). The basic memory cells are the single-junction SQUIDs, connected serially by the bit lines and inductively coupled to word lines. READ and WRITE operations are performed by sending SFQ pulses in appropriate directions along bit lines, and DC currents of appropriate polarity into word lines. This approach allows design of very dense memories with n/spl les/2 Josephson junctions per bit, memory cell area smaller than 80 /spl lambda//sup 2/ (where /spl lambda/ is the minimum feature size), and the critical parameter margin well above /spl plusmn/20%. In this paper we present the general structure of the RSFQ RAM, as well as design and results of testing of the basic memory cell and decoder circuitry using Hypres' 3.5-/spl mu/m, 1-kA/cm/sup 2/ Nb-trilayer technology.>
We have developed a novel, so-called "push-forward" design approach in Rapid Single-Flux-Quantum (RSFQ) logic. This approach leads to a more efficient circuit design at the gate level using fewer Josephson junctions combined with reasonable circuit parameter margins. Other advantages include higher operational speed and smaller power dissipation. This novel method is based on a specific type of interaction (pushing forward) between single flux quanta already stored by RSFQ gates and newly arriving data SFQ pulses. It implies a reuse of an internal gate memory as well as realization of multi-quantum storage. Using this push-forward design approach, we have designed, optimized, fabricated, and successfully tested two versions of Carry-Save Serial Adders for digital signal processing applications.>