Abstract One of the main challenges for single flux quantum (SFQ) technology to successfully implement a microprocessor is to have a compact and robust on-chip memory that can be used for register files and cache memory. In this context, we designed high capacity destructive readout (HC-DRO) cells. The design is based on our insight that each cell can store more than one SFQ pulse with the same area footprint of a regular DRO cell. In our current design, we demonstrate a single HC-DRO cell that can store up to three SFQ pulses thereby enabling us to store the equivalent of two bits of memory in a single cell. We have designed a register file (RF) architecture for a microprocessor and used the HC-DRO cells to reduce the Josephson junction count required for its implementation. The RF architecture presented in this work can also be used for implementing cache memories. We also demonstrate the benefits of doubling the storage density with HC-DRO cells by designing a 2-bit branch predictor circuit block for a 5-stage pipeline microprocessor that dramatically improves the cycles per instruction metric of an SFQ based microprocessor. All the design details are presented in the paper by verifying the design concepts through JSIM simulations and Verilog simulations.
Abstract One of the main challenges for single flux quantum (SFQ) technology to successfully implement a microprocessor is to have a compact and robust on-chip memory that can be used for register files and cache memory. In this context, we designed high capacity destructive readout (HC-DRO) cells. The design is based on our insight that each cell can store more than one SFQ pulse with the same area footprint of a regular DRO cell. In our current design, we demonstrate a single HC-DRO cell that can store up to three SFQ pulses thereby enabling us to store the equivalent of two bits of memory in a single cell. We have designed a register file (RF) architecture for a microprocessor and used the HC-DRO cells to reduce the Josephson junction count required for its implementation. The RF architecture presented in this work can also be used for implementing cache memories. We also demonstrate the benefits of doubling the storage density with HC-DRO cells by designing a 2-bit branch predictor circuit block for a 5-stage pipeline microprocessor that dramatically improves the cycles per instruction metric of an SFQ based microprocessor. All the design details are presented in the paper by verifying the design concepts through JSIM simulations and Verilog simulations.
Single Flux Quantum (SFQ) superconducting technology provides significant power and performance benefits in the era of diminishing CMOS scaling. Recent advances in design tools and fabrication facilities have brought SFQ based computing to the forefront. One challenge faced by SFQ technology is to have a compact and robust on-chip memory, which can be used for implementing register files and cache memory. While dense memories are being investigated through the development of three-terminal devices such as Nanocryotrons, in this work, we build on a novel memory cell built using traditional Josephson junctions (JJs). In particular, we design a high capacity register file, called HiPerRF, that builds on a High Capacity Destructive ReadOut (HC-DRO) cell in SFQ technology. HC-DRO design can store up to three fluxon pulses, thereby providing the equivalent of 2-bit storage in a single cell. However, these cells provide only destructive readout capability, namely each value can be read only once. However, CPU register file contents are read multiple times in any program, and hence a destructive readout complicates register file design. HiPerRF provides the non-destructive property using a loopback write mechanism, thereby preserving the higher density of HC-DRO cells without compromising the multi-read demands of a register file. HiPerRF reduces the JJ count of the register file design, after accounting for all the peripheral access circuitry costs, by 56.1% and reduces the static power by 46.2%. Furthermore, HiPerRF reduces the JJ count by 16.3% even when considering an entire in-order RISC-V CPU core.
A pipelined 8 bit-serial single-flux-quantum microprocessor integrating cache memories, called CORE1γ, has been designed and implemented. The CORE1γ has 16 byte and 8 byte shift-register-based cache memories for instructions and for data, respectively. The microprocessor overlaps four instructions in pipeline executions. The pipeline stages are optimized to control the cache memories and a new circuit component is developed to manage the pipeline execution according to whether each cache hits or misses. Advanced passive transmission line techniques with use of the cell library of the 2.5 kA cm −2 niobium standard process are utilized to implement the CORE1γ accompanied by extremely complex interconnects. The CORE1γ is made up of 295 passive interconnects, and 22302 Josephson junctions are integrated on a 6.36 × 6.36 mm 2 area. The logic simulation shows that the peak performance is estimated at 1000 million operations per second, and it is kept even during memory access as long as the cache memories hit.
Due to their high-speed operation and low power consumption, single flux quantum (SFQ) circuits are promising technologies for integrated circuits. However, current superconducting fabrication limitations impose strict area constraints, challenging the construction of large-scale systems. Unary computing (UC) encodes numerical values by concentrating all “1”s at the beginning of a bit sequence. This approach enables arithmetic operations with fewer logic gates, thereby improving the area efficiency. In this study, we propose a novel high-capacity D flip-flop (HC-DFF) cell for UC-based SFQ circuits that achieves high-density data registration while preserving UC encoding. The HC-DFF employs a cascaded storage loop structure in which each loop sequentially stores one flux quantum, avoiding the margin deterioration associated with storing multiple flux quanta in a single loop. Simulation shows that the proposed HC-DFF achieves a bias margin of –20.8% to +32.7% and supports read/write operations above 100 GHz. We fabricated the HC-DFF using a 10 kA/cm² Nb four-layer superconducting process and verified its operation through low-speed measurements. The HC-DFF offers enhanced scalability and stability while reducing the number of required Josephson junctions by 83.3% per bit compared to conventional DFF-based shift registers for saving UC signals. For short unary sequences of less than 31 bits, it retains an advantage over storing binary data with equivalent precision using conventional DFF-based shift registers.
CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and on-chip cache architectures.
In comparison to the widely-used CMOS circuits, superconducting Rapid Single Flux Quantum (RSFQ) circuits offer advantages such as fast operating frequency and low power consumption, making them a potential direction for development in the post-Moore era of digital circuits. However, designing RSFQ CPUs faces challenges, one of which is the need for a compact register file. This is because, under current RSFQ circuit process conditions, the memory module typically occupies a large chip area. This paper proposes a newly-designed Write-controllable Non-Destructive Read Out cell (WNDRO) that can limit the data writing pulse input to change the internal state of the cell. Based on the WNDRO, a compact RSFQ register file is designed that can realize random, non-destructive data reading. Additionally, a global write strategy is applied to omit the data write routing circuit and the reset control module, and the circuit design of the read and write control module is optimized. In comparison to general designs, the proposed compact register file design will save a large number of Josephson Junctions and effectively reduce the chip area. Additionally, this paper proposes several optimization logic designs for RSFQ CPU designers as a reference.
New superconductor single flux quantum (SFQ) technology, such as Reciprocal Quantum Logic (RQL), is currently considered one of the promising candidates for highperformance energy-efficient computing. This paper presents our work on the design and detailed energy efficiency analysis of three types of 32- and 64-bit RQL multi-ported pipelined local storage structures (13 total), namely 1) random access memory (RAM) and register files, 2) direct-mapped write-through and write-back caches, and 3) first-in-first-out (FIFO) buffers. Our layout-aware cell-level design process uses a VHDL RQL cell library developed at the Ultra High Speed Computing Laboratory at Stony Brook University (SBU). The SBU VHDL RQL cell library specifies the dynamic and standby energy consumption, gate delays, a number of Josephson junctions (JJs) per cell, and approximate sizes of individual cells based on the parameters of the 248 nm 100 μA/μm210 Nb metal layer SFQ fabrication process currently under development at the MIT Lincoln Laboratory. Gate and wire delays as well as clock skew are taken into account during digital circuit simulation done with Mentor Graphics CAD tools. After completing a physical chip layout, the circuit models need to be updated and re-simulated to include the effects of parasitic inductances and actual wire lengths on signal propagation delays. To meet both performance and energy efficiency targets, the RQL storage structures were designed with RQL non-destructive read-out single-bit storage cells. We chose a relatively moderate clock frequency of 8.5 GHz for all storage units to keep their read latencies in the range of 1- 3 cycles. The most complex design in terms of JJs is a tripleported 4 Kbit 64x64-bit register file with 253,918 JJs and its read access latency of 338 ps. The highest energy consumption in terms of energy/operation/bit (~9.5 aJ at 4.2 K) is for a write hit in a 2 Kbit 32-bit wide write-back cache. The average energy consumption of the RQL storage designs varies from ~1.6 aJ/operation/bit for a small 4x32-bit FIFO to 7.3 aJ/operation/bit for the 2 Kbit write-back cache at 4.2 K. Given the cryocooler efficiency of 0.1%, this means the energy consumption of ~1.6-7.3 fJ/operation/bit at room temperature. The physical implementation of the RQL storage units will become feasible upon the development of the target MIT fabrication process and CAD tools for VLSI RQL chip design in 2015-2016.