A pipelined 8 bit-serial single-flux-quantum microprocessor integrating cache memories, called CORE1γ, has been designed and implemented. The CORE1γ has 16 byte and 8 byte shift-register-based cache memories for instructions and for data, respectively. The microprocessor overlaps four instructions in pipeline executions. The pipeline stages are optimized to control the cache memories and a new circuit component is developed to manage the pipeline execution according to whether each cache hits or misses. Advanced passive transmission line techniques with use of the cell library of the 2.5 kA cm −2 niobium standard process are utilized to implement the CORE1γ accompanied by extremely complex interconnects. The CORE1γ is made up of 295 passive interconnects, and 22302 Josephson junctions are integrated on a 6.36 × 6.36 mm 2 area. The logic simulation shows that the peak performance is estimated at 1000 million operations per second, and it is kept even during memory access as long as the cache memories hit.
A pipelined 8 bit-serial single-flux-quantum microprocessor integrating cache memories, called CORE1γ, has been designed and implemented. The CORE1γ has 16 byte and 8 byte shift-register-based cache memories for instructions and for data, respectively. The microprocessor overlaps four instructions in pipeline executions. The pipeline stages are optimized to control the cache memories and a new circuit component is developed to manage the pipeline execution according to whether each cache hits or misses. Advanced passive transmission line techniques with use of the cell library of the 2.5 kA cm −2 niobium standard process are utilized to implement the CORE1γ accompanied by extremely complex interconnects. The CORE1γ is made up of 295 passive interconnects, and 22302 Josephson junctions are integrated on a 6.36 × 6.36 mm 2 area. The logic simulation shows that the peak performance is estimated at 1000 million operations per second, and it is kept even during memory access as long as the cache memories hit.
We have designed a pipelined 8-bit-serial single-flux-quantum microprocessor with multiple ALUs, called CORE1 β. In the CORE1 β, two ALUs connected in cascade enable us to perform two calculations on serial data using a register-to-register instruction, to enhance the peak performance. In addition, we have introduced pipelining to boost the performance. Although the pipelining is a difficult technique that requires a complex design in the datapath, we have implemented a simplified pipeline with seven stages by using two techniques. One is the separation of clock signals for pipelining and bit processing, and the other is the introduction of new buffers driven by independent clock signals for reading and writing flexibly in order to ease the difficulty in timing design between the register file and the ALUs. According to the logic simulation, the peak performance of the designed microprocessor is estimated to be 1500 million operations per second with a power consumption of 3.3 mW. We have fabricated the CORE1 β chip by using the NEC 2.5 kA cm −2 niobium standard process, and confirmed the correct operations of several instructions using high-speed clocks.
We have successfully demonstrated an 8-bit microprocessor using passive transmission lines based on single-flux-quantum LSI technology. In the microprocessor designed here, called CORE1/spl alpha/6, a simple bit-serial architecture with seven instructions was employed. In the CORE1/spl alpha/6, the floor plan was designed with consideration toward integration of a memory, and superconductive passive transmission lines (PTLs) were used to connect circuit blocks. Utilization of PTLs helped us reduce the propagation delay in long interconnections. The design flexibility of the floor plan was enhanced and the performance of the microprocessor was improved by 20% compared with our previous design. The CORE1/spl alpha/6 was composed of 6319 Josephson junctions and 15 PTLs with power consumption of 2.1 mW. We have confirmed the complete operations of the CORE1/spl alpha/6 by on-chip high-speed tests. The maximum clock frequencies for bit operation and instruction execution have been found to be 18 GHz and 1.2 GHz, respectively, where the performance corresponds to 240 million instructions per second (MIPS).
Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, CORE1β
A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1beta, was designed and tested. The CORE1beta has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1beta8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1beta8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1beta8 microprocessors by on-chip high-speed tests.
We describe the development of single-flux-quantum (SFQ) microprocessors and the related technologies such as designing, circuit architecture, microarchitecture, etc. Since the microprocessors studied here aim for a general-purpose computing system, we employ the complexity-reduced (CORE) architecture in which the high-speed nature of the SFQ circuits is used not for increasing processor performance but for reducing the circuit complexity. The bit-serial processing is the most suitable way to realize the CORE architecture. We assembled all the best technologies concerning SFQ integrated circuits and designed the SFQ microprocessors, CORE1α, CORE1β, and CORE1γ. The CORE1β was made up of about 11000 Josephson junctions and successfully demonstrated. The peak performance reached 1400 million operations per second with a power consumption of 3.4mW. We showed that the SFQ microprocessors had an advantage in a performance density to semiconductor's ones, which lead to the potential for constructing a high performance SFQ-circuit-based computing system.
We present a design of an 8-bit bit-serial rapid single-flux-quantum (RSFQ) microprocessor, which is called CORE e4, and its high-speed functionality test results. The CORE e4 is equipped with four general-purpose registers and can execute 20 different instructions. The first version of the CORE e4, which is called CORE e4v1, has been implemented using the National Institute of Advanced Industrial Science and Technology (AIST) 10-kA/cm2advanced process (ADP2) and the CONNECT cell library. The CORE e4v1 consists of approximately 7000 Josephson junctions and occupies a circuit area of 3.00 mm × 1.98 mm. The estimated power consumption and performance are 2.03 mW and 333 million instructions per second, respectively. CORE e4 is one of the highest performing RSFQ microprocessors.
With Moore's law approaching its physical limits, low-temperature computing technology is ushering in unprecedented development opportunities. Rapid single-flux-quantum (RSFQ) circuit technology is currently the most mature superconducting integrated circuit technology. Based on the current fabrication process, we propose an 8-bit bit-parallel RSFQ microprocessor. The proposed microprocessor processes 8-bit data each clock cycle. Ten different instructions are executed. The microprocessor mainly consists of an on-chip instruction memory, two data registers, an instruction decoder, an 8-bit bit-parallel arithmetic logic unit, and a program counter. The microprocessor contains 7702 JJs (based on the Open Dataset of CONNECT Cell Library for AIST ADP2) without considering splitters, Josephson transmission lines, and passive transmission lines. We perform a logic-level simulation of the proposed microprocessor. The simulation results show correct operation with a target frequency of 16.7 GHz.