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IEEE Transactions on Applied Superconductivity

Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, ${\rm CORE}1\beta$

Yuki Yamanashi, Masamitsu Tanaka, A. Akimoto, H. Park, Yasuhiro Kamiya, N. Irie, Nobuyuki Yoshikawa, Akira Fujimaki, Hirotaka Terai, Y. Hashimoto

Published Jun 1, 2007• 111 citations
Publisher

Abstract

A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1beta, was designed and tested. The CORE1beta has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1beta8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1beta8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1beta8 microprocessors by on-chip high-speed tests.

DOI
10.1109/tasc.2007.898606

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Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, CORE1β{\rm CORE}1\betaCORE1β
A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1beta, was designed and tested. The CORE1beta has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1beta8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1beta8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1beta8 microprocessors by on-chip high-speed tests.
We have designed a pipelined 8-bit-serial single-flux-quantum microprocessor with multiple ALUs, called CORE1 β. In the CORE1 β, two ALUs connected in cascade enable us to perform two calculations on serial data using a register-to-register instruction, to enhance the peak performance. In addition, we have introduced pipelining to boost the performance. Although the pipelining is a difficult technique that requires a complex design in the datapath, we have implemented a simplified pipeline with seven stages by using two techniques. One is the separation of clock signals for pipelining and bit processing, and the other is the introduction of new buffers driven by independent clock signals for reading and writing flexibly in order to ease the difficulty in timing design between the register file and the ALUs. According to the logic simulation, the peak performance of the designed microprocessor is estimated to be 1500 million operations per second with a power consumption of 3.3 mW. We have fabricated the CORE1 β chip by using the NEC 2.5 kA cm −2 niobium standard process, and confirmed the correct operations of several instructions using high-speed clocks.
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We present a design of an 8-bit bit-serial rapid single-flux-quantum (RSFQ) microprocessor, which is called CORE e4, and its high-speed functionality test results. The CORE e4 is equipped with four general-purpose registers and can execute 20 different instructions. The first version of the CORE e4, which is called CORE e4v1, has been implemented using the National Institute of Advanced Industrial Science and Technology (AIST) 10-kA/cm2advanced process (ADP2) and the CONNECT cell library. The CORE e4v1 consists of approximately 7000 Josephson junctions and occupies a circuit area of 3.00 mm × 1.98 mm. The estimated power consumption and performance are 2.03 mW and 333 million instructions per second, respectively. CORE e4 is one of the highest performing RSFQ microprocessors.
We have successfully demonstrated an 8-bit microprocessor using passive transmission lines based on single-flux-quantum LSI technology. In the microprocessor designed here, called CORE1/spl alpha/6, a simple bit-serial architecture with seven instructions was employed. In the CORE1/spl alpha/6, the floor plan was designed with consideration toward integration of a memory, and superconductive passive transmission lines (PTLs) were used to connect circuit blocks. Utilization of PTLs helped us reduce the propagation delay in long interconnections. The design flexibility of the floor plan was enhanced and the performance of the microprocessor was improved by 20% compared with our previous design. The CORE1/spl alpha/6 was composed of 6319 Josephson junctions and 15 PTLs with power consumption of 2.1 mW. We have confirmed the complete operations of the CORE1/spl alpha/6 by on-chip high-speed tests. The maximum clock frequencies for bit operation and instruction execution have been found to be 18 GHz and 1.2 GHz, respectively, where the performance corresponds to 240 million instructions per second (MIPS).
A microprocessor test vehicle was developed for the investigation of asynchronous design methodology for rapid- single-flux-quantum (RSFQ) circuits. We have designed and implemented a fully asynchronous RSFQ microprocessor, named SCRAM2. The data-driven self-timing (DDST) architecture is used for the design of circuit blocks of the SCRAM2. In order to ensure the logical ordering between the circuit blocks, bit-serial handshaking was adopted. The performance of the handshaking system was enhanced based on the scalable-delay-insensitive (SDI) model. The SCRAM2 is an 8-bit bit-serial microprocessor with three-stage pipelining, with a basic microarchitecture similar to that of our previously designed synchronous microprocessor, CORE1alpha. The estimated average performance of the SCRAM2 is 577 MIPS using a logic simulation. We have implemented all circuit components using the SRL 2.5 kA/cm2Nb process and confirmed their correct operation. Several operations of the SCRAM2 have been successfully confirmed.
A novel method of design for controllers of pipelined microprocessors using single-flux-quantum (SFQ) logic has been proposed. The proposed design approach is based on one hot encoding and is very suitable for designing a finite state machine using SFQ logic circuits, where each internal state of the microprocessor is represented by a flip-flop. In this approach, decoding of the internal state can be performed instantaneously, in contrast to the case in the conventional method using a binary state register. Moreover, pipelining is effectively implemented without increasing the circuit size because no pipeline registers are required in the one hot encoding. By using this method, we have designed a controller for our new SFQ microprocessors, which employs pipelining. The number of Josephson junctions of the newly designed controller is 1067, while the previous version without pipelining contains 1721 Josephson junctions. These results indicate that the proposed design approach is very effective for pipelined SFQ microprocessors. We have implemented a new controller using the NEC 2.5 kA cm −2 Nb standard process and confirmed its correct operation experimentally.