Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Superconductor Science and Technology

Design of a pipelined 8-bit-serial single-flux-quantum microprocessor with multiple ALUs

Masamitsu Tanaka, Tadashi Kawamoto, Yuki Yamanashi, Yasuhiro Kamiya, A Akimoto, K. Fujiwara, Akira Fujimaki, Nobuyuki Yoshikawa, Hirotaka Terai, Shinichi Yorozu

Published Mar 16, 2006• 35 citations
Publisher

Abstract

We have designed a pipelined 8-bit-serial single-flux-quantum microprocessor with multiple ALUs, called CORE1 β. In the CORE1 β, two ALUs connected in cascade enable us to perform two calculations on serial data using a register-to-register instruction, to enhance the peak performance. In addition, we have introduced pipelining to boost the performance. Although the pipelining is a difficult technique that requires a complex design in the datapath, we have implemented a simplified pipeline with seven stages by using two techniques. One is the separation of clock signals for pipelining and bit processing, and the other is the introduction of new buffers driven by independent clock signals for reading and writing flexibly in order to ease the difficulty in timing design between the register file and the ALUs. According to the logic simulation, the peak performance of the designed microprocessor is estimated to be 1500 million operations per second with a power consumption of 3.3 mW. We have fabricated the CORE1 β chip by using the NEC 2.5 kA cm −2 niobium standard process, and confirmed the correct operations of several instructions using high-speed clocks.

DOI
10.1088/0953-2048/19/5/s38

Related papers

Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, ${\rm CORE}1\beta$

Yuki Yamanashi, Masamitsu Tanaka, A. Akimoto +7 more

A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1beta, was designed and tested. The CORE1beta has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1beta8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1beta8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1beta8 microprocessors by on-chip high-speed tests.

IEEE Transactions on Applied Superconductivity•Jun 1, 2007•111 citations

Design and implementation of a pipelined 8 bit-serial single-flux-quantum microprocessor with cache memories

Masamitsu Tanaka, Yuki Yamanashi, N Irie +8 more

A pipelined 8 bit-serial single-flux-quantum microprocessor integrating cache memories, called CORE1γ, has been designed and implemented. The CORE1γ has 16 byte and 8 byte shift-register-based cache memories for instructions and for data, respectively. The microprocessor overlaps four instructions in pipeline executions. The pipeline stages are optimized to control the cache memories and a new circuit component is developed to manage the pipeline execution according to whether each cache hits or misses. Advanced passive transmission line techniques with use of the cell library of the 2.5 kA cm −2 niobium standard process are utilized to implement the CORE1γ accompanied by extremely complex interconnects. The CORE1γ is made up of 295 passive interconnects, and 22302 Josephson junctions are integrated on a 6.36 × 6.36 mm 2 area. The logic simulation shows that the peak performance is estimated at 1000 million operations per second, and it is kept even during memory access as long as the cache memories hit.

Superconductor Science and Technology•Oct 18, 2007•31 citations

Demonstration of a Single-Flux-Quantum Microprocessor Using Passive Transmission Lines

Masamitsu Tanaka, Takaharu Kondo, Nobuo Nakajima +10 more

We have successfully demonstrated an 8-bit microprocessor using passive transmission lines based on single-flux-quantum LSI technology. In the microprocessor designed here, called CORE1/spl alpha/6, a simple bit-serial architecture with seven instructions was employed. In the CORE1/spl alpha/6, the floor plan was designed with consideration toward integration of a memory, and superconductive passive transmission lines (PTLs) were used to connect circuit blocks. Utilization of PTLs helped us reduce the propagation delay in long interconnections. The design flexibility of the floor plan was enhanced and the performance of the microprocessor was improved by 20% compared with our previous design. The CORE1/spl alpha/6 was composed of 6319 Josephson junctions and 15 PTLs with power consumption of 2.1 mW. We have confirmed the complete operations of the CORE1/spl alpha/6 by on-chip high-speed tests. The maximum clock frequencies for bit operation and instruction execution have been found to be 18 GHz and 1.2 GHz, respectively, where the performance corresponds to 240 million instructions per second (MIPS).

IEEE Transactions on Applied Superconductivity•Jun 1, 2005•73 citations

Bit-Serial Single Flux Quantum Microprocessor CORE

Akira Fujimaki, Masamitsu Tanaka, Takahiro Yamada +3 more

We describe the development of single-flux-quantum (SFQ) microprocessors and the related technologies such as designing, circuit architecture, microarchitecture, etc. Since the microprocessors studied here aim for a general-purpose computing system, we employ the complexity-reduced (CORE) architecture in which the high-speed nature of the SFQ circuits is used not for increasing processor performance but for reducing the circuit complexity. The bit-serial processing is the most suitable way to realize the CORE architecture. We assembled all the best technologies concerning SFQ integrated circuits and designed the SFQ microprocessors, CORE1α, CORE1β, and CORE1γ. The CORE1β was made up of about 11000 Josephson junctions and successfully demonstrated. The peak performance reached 1400 million operations per second with a power consumption of 3.4mW. We showed that the SFQ microprocessors had an advantage in a performance density to semiconductor's ones, which lead to the potential for constructing a high performance SFQ-circuit-based computing system.

IEICE Transactions on Electronics•Mar 1, 2008•97 citations

Design of Datapath Circuits for a Bit-Parallel 8-bit RSFQ Microprocessor

Pei-Yao Qu, Guang-Ming Tang, Xiaochun Ye +3 more

Rapid single-flux-quantum (RSFQ) is expected to be the next generation integrated circuit technology because of its ultra-high-speed with ultra-low-power consumption. We propose datapath circuits for an 8-bit bit-parallel RSFQ microprocessor. The proposed datapath circuits process 8-bit data each clock cycle. Seven instructions are executed in the datapath, including ADD, ADDI, IN, OUT, LOADI, SRL and MOV. The datapath circuits consist of eight input ports, eight output ports, five multiplexers (MUXs), two 8-bit data registers and one 8-bit bit-parallel arithmetic logic unit (ALU). The datapath circuits contain 12 pipeline stages and 2993 JJs based on the Open Dataset of CONNECT Cell Library for AIST ADP2 without considering wiring cells. We perform digital simulation of the proposed datapath circuits. The simulation results show correct operation with the assumed frequency of 20 GHz.

IEEE International Superconductive Electronics Conference (ISEC)•Jul 1, 2019•3 citations

Design and Demonstration of an 8-bit Bit-Serial RSFQ Microprocessor: CORE e4

Yuki Ando, Ryo Sato, Masamitsu Tanaka +3 more

We present a design of an 8-bit bit-serial rapid single-flux-quantum (RSFQ) microprocessor, which is called CORE e4, and its high-speed functionality test results. The CORE e4 is equipped with four general-purpose registers and can execute 20 different instructions. The first version of the CORE e4, which is called CORE e4v1, has been implemented using the National Institute of Advanced Industrial Science and Technology (AIST) 10-kA/cm2advanced process (ADP2) and the CONNECT cell library. The CORE e4v1 consists of approximately 7000 Josephson junctions and occupies a circuit area of 3.00 mm × 1.98 mm. The estimated power consumption and performance are 2.03 mW and 333 million instructions per second, respectively. CORE e4 is one of the highest performing RSFQ microprocessors.

IEEE Transactions on Applied Superconductivity•May 10, 2016•100 citations
We have designed a pipelined 8-bit-serial single-flux-quantum microprocessor with multiple ALUs, called CORE1 β. In the CORE1 β, two ALUs connected in cascade enable us to perform two calculations on serial data using a register-to-register instruction, to enhance the peak performance. In addition, we have introduced pipelining to boost the performance. Although the pipelining is a difficult technique that requires a complex design in the datapath, we have implemented a simplified pipeline with seven stages by using two techniques. One is the separation of clock signals for pipelining and bit processing, and the other is the introduction of new buffers driven by independent clock signals for reading and writing flexibly in order to ease the difficulty in timing design between the register file and the ALUs. According to the logic simulation, the peak performance of the designed microprocessor is estimated to be 1500 million operations per second with a power consumption of 3.3 mW. We have fabricated the CORE1 β chip by using the NEC 2.5 kA cm −2 niobium standard process, and confirmed the correct operations of several instructions using high-speed clocks.
Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, CORE1β{\rm CORE}1\betaCORE1β
A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1beta, was designed and tested. The CORE1beta has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1beta8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1beta8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1beta8 microprocessors by on-chip high-speed tests.
A pipelined 8 bit-serial single-flux-quantum microprocessor integrating cache memories, called CORE1γ, has been designed and implemented. The CORE1γ has 16 byte and 8 byte shift-register-based cache memories for instructions and for data, respectively. The microprocessor overlaps four instructions in pipeline executions. The pipeline stages are optimized to control the cache memories and a new circuit component is developed to manage the pipeline execution according to whether each cache hits or misses. Advanced passive transmission line techniques with use of the cell library of the 2.5 kA cm −2 niobium standard process are utilized to implement the CORE1γ accompanied by extremely complex interconnects. The CORE1γ is made up of 295 passive interconnects, and 22302 Josephson junctions are integrated on a 6.36 × 6.36 mm 2 area. The logic simulation shows that the peak performance is estimated at 1000 million operations per second, and it is kept even during memory access as long as the cache memories hit.
We have successfully demonstrated an 8-bit microprocessor using passive transmission lines based on single-flux-quantum LSI technology. In the microprocessor designed here, called CORE1/spl alpha/6, a simple bit-serial architecture with seven instructions was employed. In the CORE1/spl alpha/6, the floor plan was designed with consideration toward integration of a memory, and superconductive passive transmission lines (PTLs) were used to connect circuit blocks. Utilization of PTLs helped us reduce the propagation delay in long interconnections. The design flexibility of the floor plan was enhanced and the performance of the microprocessor was improved by 20% compared with our previous design. The CORE1/spl alpha/6 was composed of 6319 Josephson junctions and 15 PTLs with power consumption of 2.1 mW. We have confirmed the complete operations of the CORE1/spl alpha/6 by on-chip high-speed tests. The maximum clock frequencies for bit operation and instruction execution have been found to be 18 GHz and 1.2 GHz, respectively, where the performance corresponds to 240 million instructions per second (MIPS).
We describe the development of single-flux-quantum (SFQ) microprocessors and the related technologies such as designing, circuit architecture, microarchitecture, etc. Since the microprocessors studied here aim for a general-purpose computing system, we employ the complexity-reduced (CORE) architecture in which the high-speed nature of the SFQ circuits is used not for increasing processor performance but for reducing the circuit complexity. The bit-serial processing is the most suitable way to realize the CORE architecture. We assembled all the best technologies concerning SFQ integrated circuits and designed the SFQ microprocessors, CORE1α, CORE1β, and CORE1γ. The CORE1β was made up of about 11000 Josephson junctions and successfully demonstrated. The peak performance reached 1400 million operations per second with a power consumption of 3.4mW. We showed that the SFQ microprocessors had an advantage in a performance density to semiconductor's ones, which lead to the potential for constructing a high performance SFQ-circuit-based computing system.
Rapid single-flux-quantum (RSFQ) is expected to be the next generation integrated circuit technology because of its ultra-high-speed with ultra-low-power consumption. We propose datapath circuits for an 8-bit bit-parallel RSFQ microprocessor. The proposed datapath circuits process 8-bit data each clock cycle. Seven instructions are executed in the datapath, including ADD, ADDI, IN, OUT, LOADI, SRL and MOV. The datapath circuits consist of eight input ports, eight output ports, five multiplexers (MUXs), two 8-bit data registers and one 8-bit bit-parallel arithmetic logic unit (ALU). The datapath circuits contain 12 pipeline stages and 2993 JJs based on the Open Dataset of CONNECT Cell Library for AIST ADP2 without considering wiring cells. We perform digital simulation of the proposed datapath circuits. The simulation results show correct operation with the assumed frequency of 20 GHz.
We present a design of an 8-bit bit-serial rapid single-flux-quantum (RSFQ) microprocessor, which is called CORE e4, and its high-speed functionality test results. The CORE e4 is equipped with four general-purpose registers and can execute 20 different instructions. The first version of the CORE e4, which is called CORE e4v1, has been implemented using the National Institute of Advanced Industrial Science and Technology (AIST) 10-kA/cm2advanced process (ADP2) and the CONNECT cell library. The CORE e4v1 consists of approximately 7000 Josephson junctions and occupies a circuit area of 3.00 mm × 1.98 mm. The estimated power consumption and performance are 2.03 mW and 333 million instructions per second, respectively. CORE e4 is one of the highest performing RSFQ microprocessors.