We present a design of an 8-bit bit-serial rapid single-flux-quantum (RSFQ) microprocessor, which is called CORE e4, and its high-speed functionality test results. The CORE e4 is equipped with four general-purpose registers and can execute 20 different instructions. The first version of the CORE e4, which is called CORE e4v1, has been implemented using the National Institute of Advanced Industrial Science and Technology (AIST) 10-kA/cm2advanced process (ADP2) and the CONNECT cell library. The CORE e4v1 consists of approximately 7000 Josephson junctions and occupies a circuit area of 3.00 mm × 1.98 mm. The estimated power consumption and performance are 2.03 mW and 333 million instructions per second, respectively. CORE e4 is one of the highest performing RSFQ microprocessors.
We present a design of an 8-bit bit-serial rapid single-flux-quantum (RSFQ) microprocessor, which is called CORE e4, and its high-speed functionality test results. The CORE e4 is equipped with four general-purpose registers and can execute 20 different instructions. The first version of the CORE e4, which is called CORE e4v1, has been implemented using the National Institute of Advanced Industrial Science and Technology (AIST) 10-kA/cm2advanced process (ADP2) and the CONNECT cell library. The CORE e4v1 consists of approximately 7000 Josephson junctions and occupies a circuit area of 3.00 mm × 1.98 mm. The estimated power consumption and performance are 2.03 mW and 333 million instructions per second, respectively. CORE e4 is one of the highest performing RSFQ microprocessors.
We report recent progress in the development of rapid single-flux-quantum (RSFQ) microprocessors integrated with random access memories (RAMs) based on bit-serial processing, called CORE e series. The bit-serial processing is an efficient, unique approach for RSFQ microprocessors that target ultrafast clock frequency with small hardware size. The CORE e series have a richer instruction set and RAMs integrated on the same die, and are capable of running small-scale benchmark programs. We are currently developing three microprocessors in parallel, CORE e2, e3, and e4, for different purposes including prototype demonstration, investigation on efficient use of hardware and energy, and full-function implementation. Here we describe design and implementation of the CORE e microprocessors together with a high-density shift-register-based RAM. The estimated performance of these microprocessors is 333 million instructions per second (MIPS) with 4.6-5.6 mW power.
We demonstrated a high-density shift-register-based random access memory system based on rapid single-flux-quantum (RSFQ) logic. This memory system was developed to be integrated with bit-serial RSFQ microprocessors, which are called the CORE e series. It is composed of a shift-register array to store data, a decoder to select the shift register pointed to by a given address, and mergers to output data. To achieve high density, we introduced a new memory system structure and designed compact storage elements and other peripheral components. We integrated two 256-bit memory systems (32 entries for 8-bit data and instructions each) with a CORE e microprocessor and fabricated it using the National Institute of Advanced Industrial Science and Technology 10-kA/cm2Advanced Process. The area occupied by each memory system is 2.69 mm2. We obtained correct operations for all of the addresses in low-frequency tests. The typical measured bias margin was 86%-106%.
Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, CORE1β
A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1beta, was designed and tested. The CORE1beta has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1beta8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1beta8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1beta8 microprocessors by on-chip high-speed tests.
We present design and experimental results of a rapid single-flux-quantum (RSFQ) bit-serial microprocessor with reduced-size embedded random access memories (RAMs) and with a minimal instruction set, called CORE e2h. The microprocessors called CORE e series have been developed for demonstrating small-scale program execution, such as loop calculation and sorting, in order to show the first prototype of a stored-program computer using the RSFQ technology. The CORE e2h is the most simplified variation of the CORE e series, which is equipped with only two registers, and can execute 13 instructions. The target clock frequency for bit-serial operation is 50 GHz, while the designed system clock cycle is 2 GHz. We carefully designed every component, implementing functionality using a small number of Josephson junctions with a small footprint. We fabricated several chips of the CORE e2h microprocessor integrated with two 128-bit shift-register-based RAMs on the same die. We experimentally obtained correct operations for all the instructions, and confirmed high-speed transfer between the instruction memory and controller unit and between the data memory and datapath at around 50 GHz.
With Moore's law approaching its physical limits, low-temperature computing technology is ushering in unprecedented development opportunities. Rapid single-flux-quantum (RSFQ) circuit technology is currently the most mature superconducting integrated circuit technology. Based on the current fabrication process, we propose an 8-bit bit-parallel RSFQ microprocessor. The proposed microprocessor processes 8-bit data each clock cycle. Ten different instructions are executed. The microprocessor mainly consists of an on-chip instruction memory, two data registers, an instruction decoder, an 8-bit bit-parallel arithmetic logic unit, and a program counter. The microprocessor contains 7702 JJs (based on the Open Dataset of CONNECT Cell Library for AIST ADP2) without considering splitters, Josephson transmission lines, and passive transmission lines. We perform a logic-level simulation of the proposed microprocessor. The simulation results show correct operation with a target frequency of 16.7 GHz.
Rapid single-flux-quantum (RSFQ) is expected to be the next generation integrated circuit technology because of its ultra-high-speed with ultra-low-power consumption. We propose datapath circuits for an 8-bit bit-parallel RSFQ microprocessor. The proposed datapath circuits process 8-bit data each clock cycle. Seven instructions are executed in the datapath, including ADD, ADDI, IN, OUT, LOADI, SRL and MOV. The datapath circuits consist of eight input ports, eight output ports, five multiplexers (MUXs), two 8-bit data registers and one 8-bit bit-parallel arithmetic logic unit (ALU). The datapath circuits contain 12 pipeline stages and 2993 JJs based on the Open Dataset of CONNECT Cell Library for AIST ADP2 without considering wiring cells. We perform digital simulation of the proposed datapath circuits. The simulation results show correct operation with the assumed frequency of 20 GHz.