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IEEE International Superconductive Electronics Conference (ISEC)

Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories

Masamitsu Tanaka, Takata Kensuke, Takahiro Kawaguchi, Yuki Ando, Nobuyuki Yoshikawa, Ryo Sato, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi

Published Jul 1, 2015• 13 citations
Publisher

Abstract

We report recent progress in the development of rapid single-flux-quantum (RSFQ) microprocessors integrated with random access memories (RAMs) based on bit-serial processing, called CORE e series. The bit-serial processing is an efficient, unique approach for RSFQ microprocessors that target ultrafast clock frequency with small hardware size. The CORE e series have a richer instruction set and RAMs integrated on the same die, and are capable of running small-scale benchmark programs. We are currently developing three microprocessors in parallel, CORE e2, e3, and e4, for different purposes including prototype demonstration, investigation on efficient use of hardware and energy, and full-function implementation. Here we describe design and implementation of the CORE e microprocessors together with a high-density shift-register-based RAM. The estimated performance of these microprocessors is 333 million instructions per second (MIPS) with 4.6-5.6 mW power.

DOI
10.1109/isec.2015.7383449

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We report recent progress in the development of rapid single-flux-quantum (RSFQ) microprocessors integrated with random access memories (RAMs) based on bit-serial processing, called CORE e series. The bit-serial processing is an efficient, unique approach for RSFQ microprocessors that target ultrafast clock frequency with small hardware size. The CORE e series have a richer instruction set and RAMs integrated on the same die, and are capable of running small-scale benchmark programs. We are currently developing three microprocessors in parallel, CORE e2, e3, and e4, for different purposes including prototype demonstration, investigation on efficient use of hardware and energy, and full-function implementation. Here we describe design and implementation of the CORE e microprocessors together with a high-density shift-register-based RAM. The estimated performance of these microprocessors is 333 million instructions per second (MIPS) with 4.6-5.6 mW power.
We present design and experimental results of a rapid single-flux-quantum (RSFQ) bit-serial microprocessor with reduced-size embedded random access memories (RAMs) and with a minimal instruction set, called CORE e2h. The microprocessors called CORE e series have been developed for demonstrating small-scale program execution, such as loop calculation and sorting, in order to show the first prototype of a stored-program computer using the RSFQ technology. The CORE e2h is the most simplified variation of the CORE e series, which is equipped with only two registers, and can execute 13 instructions. The target clock frequency for bit-serial operation is 50 GHz, while the designed system clock cycle is 2 GHz. We carefully designed every component, implementing functionality using a small number of Josephson junctions with a small footprint. We fabricated several chips of the CORE e2h microprocessor integrated with two 128-bit shift-register-based RAMs on the same die. We experimentally obtained correct operations for all the instructions, and confirmed high-speed transfer between the instruction memory and controller unit and between the data memory and datapath at around 50 GHz.
We demonstrated a high-density shift-register-based random access memory system based on rapid single-flux-quantum (RSFQ) logic. This memory system was developed to be integrated with bit-serial RSFQ microprocessors, which are called the CORE e series. It is composed of a shift-register array to store data, a decoder to select the shift register pointed to by a given address, and mergers to output data. To achieve high density, we introduced a new memory system structure and designed compact storage elements and other peripheral components. We integrated two 256-bit memory systems (32 entries for 8-bit data and instructions each) with a CORE e microprocessor and fabricated it using the National Institute of Advanced Industrial Science and Technology 10-kA/cm2Advanced Process. The area occupied by each memory system is 2.69 mm2. We obtained correct operations for all of the addresses in low-frequency tests. The typical measured bias margin was 86%-106%.
We present a design of an 8-bit bit-serial rapid single-flux-quantum (RSFQ) microprocessor, which is called CORE e4, and its high-speed functionality test results. The CORE e4 is equipped with four general-purpose registers and can execute 20 different instructions. The first version of the CORE e4, which is called CORE e4v1, has been implemented using the National Institute of Advanced Industrial Science and Technology (AIST) 10-kA/cm2advanced process (ADP2) and the CONNECT cell library. The CORE e4v1 consists of approximately 7000 Josephson junctions and occupies a circuit area of 3.00 mm × 1.98 mm. The estimated power consumption and performance are 2.03 mW and 333 million instructions per second, respectively. CORE e4 is one of the highest performing RSFQ microprocessors.
We report an energy-efficient bit-serial microprocessor based on single-flux-quantum (SFQ) logic, called CORE e3, using a low-voltage bias technique. This microprocessor was designed for integrating memories, and we developed it to investigate the efficient use of hardware and energy, using the low-voltage rapid single-flux-quantum (LV-RSFQ) technique. We implemented the CORE e3 and its test circuit using a 10-kA/cm2Nb process. We confirmed via logic simulations that all instructions were executed correctly with a 1-GHz system clock. We expect a 3.51 fold improvement in energy efficiency.
We have demonstrated the execution of several programs stored in an instruction memory by a rapid single-flux-quantum bit-serial 8-bit microprocessor named CORE e2h. We employed a minimal instruction set architecture composed of 13 instructions based on the reduced instruction set computer. We integrated a 128-bit instruction memory and a 128-bit data memory with an arithmetic logic unit, two registers, a program counter, an instruction register, and a controller unit on a single chip. The bit-serial operation was performed by an on-chip clock generator, while the system clocks are provided from room-temperature electronics. The CORE e2h was made up of 11 000 Nb/AlOx/Nb Josephson junctions and fabricated with the Advanced Industrial Science and Technology 10-kA/cm2, 9-Nb-layer process. We obtained the correct results for all the executed programs, including the integer division, the two kinds of summation algorithms, the Euclidean algorithm, and finding the greatest divisor. These test programs contained a single or nested double loop, and the maximum number of executed instructions was 205. We confirmed the stable operation with the DC bias margins of around 10% at 50-GHz for different test programs. The measured electric power consumption was 2.5 mW at 4.2 K, and the estimated computing power was 500 × 106 instructions/s.