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IEEE Transactions on Applied Superconductivity

Design of an RSFQ microprocessor

P. Bunyk, Vasili K. Semenov

Published Jun 1, 1995• 13 citations
Publisher

Abstract

We are discussing a general-purpose microprocessor architecture that is suitable for implementation using the Rapid Single-Flux-Quantum (RSFQ) family of logic-memory circuits. While the microprocessor provides a functionally complete RISC instruction set with 16-bit words, a bit-serial self-timed approach makes it simple enough to be fabricated using the current Josephson junction technology. Our plans are to design, fabricate and test a completely operational prototype of this system.>

DOI
10.1109/77.403303

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With Moore's law approaching its physical limits, low-temperature computing technology is ushering in unprecedented development opportunities. Rapid single-flux-quantum (RSFQ) circuit technology is currently the most mature superconducting integrated circuit technology. Based on the current fabrication process, we propose an 8-bit bit-parallel RSFQ microprocessor. The proposed microprocessor processes 8-bit data each clock cycle. Ten different instructions are executed. The microprocessor mainly consists of an on-chip instruction memory, two data registers, an instruction decoder, an 8-bit bit-parallel arithmetic logic unit, and a program counter. The microprocessor contains 7702 JJs (based on the Open Dataset of CONNECT Cell Library for AIST ADP2) without considering splitters, Josephson transmission lines, and passive transmission lines. We perform a logic-level simulation of the proposed microprocessor. The simulation results show correct operation with a target frequency of 16.7 GHz.
We present design and experimental results of a rapid single-flux-quantum (RSFQ) bit-serial microprocessor with reduced-size embedded random access memories (RAMs) and with a minimal instruction set, called CORE e2h. The microprocessors called CORE e series have been developed for demonstrating small-scale program execution, such as loop calculation and sorting, in order to show the first prototype of a stored-program computer using the RSFQ technology. The CORE e2h is the most simplified variation of the CORE e series, which is equipped with only two registers, and can execute 13 instructions. The target clock frequency for bit-serial operation is 50 GHz, while the designed system clock cycle is 2 GHz. We carefully designed every component, implementing functionality using a small number of Josephson junctions with a small footprint. We fabricated several chips of the CORE e2h microprocessor integrated with two 128-bit shift-register-based RAMs on the same die. We experimentally obtained correct operations for all the instructions, and confirmed high-speed transfer between the instruction memory and controller unit and between the data memory and datapath at around 50 GHz.
The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.
We report recent progress in the development of rapid single-flux-quantum (RSFQ) microprocessors integrated with random access memories (RAMs) based on bit-serial processing, called CORE e series. The bit-serial processing is an efficient, unique approach for RSFQ microprocessors that target ultrafast clock frequency with small hardware size. The CORE e series have a richer instruction set and RAMs integrated on the same die, and are capable of running small-scale benchmark programs. We are currently developing three microprocessors in parallel, CORE e2, e3, and e4, for different purposes including prototype demonstration, investigation on efficient use of hardware and energy, and full-function implementation. Here we describe design and implementation of the CORE e microprocessors together with a high-density shift-register-based RAM. The estimated performance of these microprocessors is 333 million instructions per second (MIPS) with 4.6-5.6 mW power.
The first single-chip superconductor FLUX-1 microprocessor prototype with a target clock frequency of 17-20 GHz has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using low- temperature 4 kA/cm', 1.75-pm Nb/AlOx/Nb Josephson junction technology. A FLUX-1 chip represents an %bit deeply pipelined microprocessor with a new parallel partitioned architecture that has been developed to tolerate interconnect delays and fill long FLUX-1 pipelines with operations. A FLUX-1 chip contains 65,759 Josephson junctions on a 10.6 mm x 13.2 mm die with flip-chip packaging. First FLUX-I chips fabricated in 2001 are currently under testing at TRW.