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Superconductor Science and Technology

A new design approach for control circuits of pipelined single-flux-quantum microprocessors

Yuki Yamanashi, A Akimoto, Nobuyuki Yoshikawa, Masamitsu Tanaka, Tadashi Kawamoto, Yasuhiro Kamiya, Akira Fujimaki, Hirotaka Terai, Shinichi Yorozu

Published Mar 16, 2006• 5 citations
Publisher

Abstract

A novel method of design for controllers of pipelined microprocessors using single-flux-quantum (SFQ) logic has been proposed. The proposed design approach is based on one hot encoding and is very suitable for designing a finite state machine using SFQ logic circuits, where each internal state of the microprocessor is represented by a flip-flop. In this approach, decoding of the internal state can be performed instantaneously, in contrast to the case in the conventional method using a binary state register. Moreover, pipelining is effectively implemented without increasing the circuit size because no pipeline registers are required in the one hot encoding. By using this method, we have designed a controller for our new SFQ microprocessors, which employs pipelining. The number of Josephson junctions of the newly designed controller is 1067, while the previous version without pipelining contains 1721 Josephson junctions. These results indicate that the proposed design approach is very effective for pipelined SFQ microprocessors. We have implemented a new controller using the NEC 2.5 kA cm −2 Nb standard process and confirmed its correct operation experimentally.

DOI
10.1088/0953-2048/19/5/s37

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IEEE Transactions on Applied Superconductivity•Jun 1, 1999•18 citations
A novel method of design for controllers of pipelined microprocessors using single-flux-quantum (SFQ) logic has been proposed. The proposed design approach is based on one hot encoding and is very suitable for designing a finite state machine using SFQ logic circuits, where each internal state of the microprocessor is represented by a flip-flop. In this approach, decoding of the internal state can be performed instantaneously, in contrast to the case in the conventional method using a binary state register. Moreover, pipelining is effectively implemented without increasing the circuit size because no pipeline registers are required in the one hot encoding. By using this method, we have designed a controller for our new SFQ microprocessors, which employs pipelining. The number of Josephson junctions of the newly designed controller is 1067, while the previous version without pipelining contains 1721 Josephson junctions. These results indicate that the proposed design approach is very effective for pipelined SFQ microprocessors. We have implemented a new controller using the NEC 2.5 kA cm −2 Nb standard process and confirmed its correct operation experimentally.
Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, CORE1β{\rm CORE}1\betaCORE1β
A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1beta, was designed and tested. The CORE1beta has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1beta8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1beta8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1beta8 microprocessors by on-chip high-speed tests.
A methodology for designing single-flux-quantum (SFQ) flip-flops composed of both conventional (0-) and π -shifted Josephson junctions is investigated. We investigated the implementation of a storage loop, which can store flux quantum and is indispensable to express binary logic states in superconductor logic circuits. As all SFQ flip-flops have storage loops, the investigated design methodology can be applied to their design. We designed several SFQ flip-flops composed of 0- and π -shifted Josephson junctions using the investigated design methodology. The performances of the designed SFQ flip-flops were quantitatively evaluated by using an analog circuit simulator which we developed. We confirmed the correct operation of various SFQ flip-flops composed of 0- and π -shifted Josephson junctions with wide operating margins. Moreover, we observed that the investigated design methodology is suitable for SFQ flip-flops with complementary outputs because a storage loop composed of both 0- and π -shifted Josephson junctions has a symmetric structure and the complementary output function can be realized by using the storage loop. Our investigation indicates that the number of Josephson junctions and static power consumption of a non-destructive read-out flip-flop with complementary outputs (NDROC) can be reduced to less than half of those of the conventional NDROC, which has two storage loops composed of 0-Josephson junctions, to realize the complementary output function. The investigated design methodology is expected to be applied to not only SFQ circuits but also other superconducting logic circuits and novel reconfigurable logic devices using programmable 0- π Josephson junctions.
We have designed a pipelined 8-bit-serial single-flux-quantum microprocessor with multiple ALUs, called CORE1 β. In the CORE1 β, two ALUs connected in cascade enable us to perform two calculations on serial data using a register-to-register instruction, to enhance the peak performance. In addition, we have introduced pipelining to boost the performance. Although the pipelining is a difficult technique that requires a complex design in the datapath, we have implemented a simplified pipeline with seven stages by using two techniques. One is the separation of clock signals for pipelining and bit processing, and the other is the introduction of new buffers driven by independent clock signals for reading and writing flexibly in order to ease the difficulty in timing design between the register file and the ALUs. According to the logic simulation, the peak performance of the designed microprocessor is estimated to be 1500 million operations per second with a power consumption of 3.3 mW. We have fabricated the CORE1 β chip by using the NEC 2.5 kA cm −2 niobium standard process, and confirmed the correct operations of several instructions using high-speed clocks.
A pipelined 8 bit-serial single-flux-quantum microprocessor integrating cache memories, called CORE1γ, has been designed and implemented. The CORE1γ has 16 byte and 8 byte shift-register-based cache memories for instructions and for data, respectively. The microprocessor overlaps four instructions in pipeline executions. The pipeline stages are optimized to control the cache memories and a new circuit component is developed to manage the pipeline execution according to whether each cache hits or misses. Advanced passive transmission line techniques with use of the cell library of the 2.5 kA cm −2 niobium standard process are utilized to implement the CORE1γ accompanied by extremely complex interconnects. The CORE1γ is made up of 295 passive interconnects, and 22302 Josephson junctions are integrated on a 6.36 × 6.36 mm 2 area. The logic simulation shows that the peak performance is estimated at 1000 million operations per second, and it is kept even during memory access as long as the cache memories hit.
We will propose a new design approach for single-flux-quantum (SFQ) logic circuits based on a binary decision diagram (BDD). The BDD is a way to represent a logical function by using a directed graph, which is composed of nodes having one input (root) and two outputs (branches). The node has binary states internally which can be controlled from outside, and it switches a messenger entering from the root into one of two branches depending on the internal state. It has been proven that any combinational logic can be represented by this basic element. We will show that the BDD is effectively implemented by an SFQ circuit, where the node is replaced with an SFQ D/sub 2/ flip-flop. Important features of the BDD SFQ logic circuit are simplicity of circuit structure, self-timed nature and high modularity. We have designed a BDD SFQ adder and showed that the junction count and latency are smaller than that of the conventional RSFQ adder.