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Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

A 4 b Josephson data processor chip

Y. Hatano, H. Mori, Hironao YAMADA, Hideyuki Nagaishi, H. Nakane, Mutsuo Hirano, Ushio KAWABE

Published Jan 13, 2003• 7 citations
Publisher

Abstract

The authors describe a 4-bit Josephson data processor chip featuring on-chip control and data paths and near-GHz capability. It is a closed, stand-alone chip comprising a 4-bit data path and a control path and is aimed at high-speed digital signal processing. The die is 0.5 mm square, including pads, is fabricated using 2.5- mu m-rule Nb/AlO/sub x//Nb technology, and consists of 8454 Josephson junctions and 9027 resistors. The cross-shaped junction structure realizes critical current scattering of +or-6%, and a junction characteristic voltage V/sub m/ of 50 mV. A block diagram of the Josephson data processor is shown.>

DOI
10.1109/isscc.1989.48270

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International Journal of High Speed Electronics and Systems•Jun 1, 2002•8 citations
The authors describe a 4-bit Josephson data processor chip featuring on-chip control and data paths and near-GHz capability. It is a closed, stand-alone chip comprising a 4-bit data path and a control path and is aimed at high-speed digital signal processing. The die is 0.5 mm square, including pads, is fabricated using 2.5- mu m-rule Nb/AlO/sub x//Nb technology, and consists of 8454 Josephson junctions and 9027 resistors. The cross-shaped junction structure realizes critical current scattering of +or-6%, and a junction characteristic voltage V/sub m/ of 50 mV. A block diagram of the Josephson data processor is shown.>
A 1-GHz-clock Josephson microcomputer system was developed to demonstrate the possibility of a high-speed superconducting computer system. It consists of a 4-b data processor chip and a 1-kb RAM chip. For the fabrication of these Josephson integrated circuits, a cross-shaped Nb-AlO/sub x/-Nb Josephson junction process was developed in order to realize small junction size and improve critical current uniformity, and has made fabrication of LSIs with several thousand gates possible. A latchup-free DC flip-flop is an important element in the high-speed Josephson logic and memory circuits, having been applied to an all-DC-powered Josephson RAM with asynchronous access capability. A low-inductance chip-to-chip carrier is an architectural and design concept for the Josephson computer's 1-GHz-clock operation, suppressing the crosstalk between the AC power and the output signals. Each chip is 7 mm square and is fabricated using a 2.5- mu m-rule Nb-AlO/sub x/-Nb junction process. The chips are connected on a superconducting carrier by solder bumps in a die size of 15 mm by 25 mm. The system is constructed from 8123 Josephson interferometer devices and is operable in a 1-ns cycle with 50-mW power dissipation.
We report the development of a 256-stage, one-bit superconducting digital correlator functionally tested at a highest clock frequency of 10.232 GHz and data rate of 1.279 Gb/s. The correlator consists of two 256-bit shift registers for delay and storage, 256 exclusive-OR gates for multiplication, and 256 shunted SQUID's to produce an analog summing output. It is fabricated using a Nb/AlO/sub x//Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The 5-mm square chip uses about 4350 Nb/AlO/sub x//Nb Josephson junctions and consumes about 0.4 mW.>
We describe a Josephson amplifier fabricated in a high-J/sub c/ process, which is operational to speeds of at least 10 GHz, the highest reported for a voltage-state amplifier. The amplifier converts /spl sim/200 /spl mu/V digital signals to /spl sim/5 mV at 10 GHz and could be used as an interface between two superconducting systems. The bit-error-rate of the circuit was /spl sim/5/spl times/10/sup -12/ at 5 GHz, the lowest reported; bit-error-rate measurements at 10 GHz were not possible. A high-J/sub c/ process which was used to fabricate the amplifier was developed at UC Berkeley with extremely low I/sub c/ spreads; at /spl sim/9.4 kA/cm/sup 2/ /spl sigma/ as low as 0.6% was observed. At /spl sim/10 kA/cm/sup 2/, the typical junction linear dimensions are 1.5 /spl sim/ 2 /spl mu/m, sizes for which it is not possible-with available tools-to make reliable vias that are smaller than the junction. We use a nonplanarized junction process, where the via for contact of a wiring layer to a junction can be larger than the junction.
For reliable fabrication of Nb/AlO/sub x//Nb Josephson integrated circuits, a combination of anodization and reactive ion etching techniques was used to make various sizes of high-quality Nb/AlO/sub x//Nb Josephson tunnel junctions with J/sub c/ as high as 5000 A/cm/sup 2/ and V/sub m/(2 mV) as large as 60 mV at 4.2 K. A ten-level process on Nb/AlO/sub x//Nb trilayers with J/sub c/ of 1500 A/cm/sup 2/ was used to fabricate a functional 12-b A/D converter. This circuit included 2.7- mu m-diameter junctions defined by anodization and 5- mu m-diameter junctions defined by reactive ion etching using Nb/sub 2/O/sub 5/ and Al as etch stops. A lift-off process with image-reversal photoresist was used to define SiO/sub 2/ insulators, Mo resistors, and Au resistors. Mo resistor values were adjusted by reactive ion etching. Measurements of the completed circuit show that all circuit components had correct values to well within design tolerance.
The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.