IEEE Transactions on Magnetics

Josephson shift register design and layout

John X. Przybysz, Richard D. Blaugher, J. Buttyan

Published Mar 1, 1989• 14 citations

Abstract

Integrated circuit chips were designed and fabricated, based on a Josephson shift register circuit that simulated operation at 25 GHz using the SPICE program. The 6.25-mm/sup 2/ chip featured a twelve-gate, four-stage shift register fabricated with Nb/AlO/sub x//Nb Josephson junctions with a design value of 2000 A/cm/sup 2/ critical current density. SUPERCOMPACT, a general program for the design of monolithic microwave integrated circuits, was used to model the effects of layout geometry on the uniformity and phase coherence of logic gate bias currents. A layout geometry for the superconductive transmission lines and thin-film bias resistors was developed. The original SPICE-designed circuit was modified as a result of these calculations. Modeling indicated that bias current variations could be limited to 3% for all possible logic states of the shift register, and phase coherence of the gates could be maintained to within 2 degrees at 10 GHz. The fundamental soundness of the circuit design was demonstrated by the proper operation of fabricated shift registers.>

DOI: 10.1109/20.92416

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