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IEEE Transactions on Magnetics

A fast Josephson SFQ shift register

F. Kuo, Stephen R. Whiteley, S. M. Faris

Published Mar 1, 1989• 4 citations
Publisher

Abstract

A Josephson SFQ (single flux quantum) shift register circuit operating under a two-phase power was designed and tested. The test cell was fabricated using the Nb/AlO/sub x//Nb junction SNEAP process. The main data latch is DC biased; the data storage is accomplished by the transfer of a single flux quantum in or out of a SQUID (superconducting quantum interference device) superconducting loop. A two-phase sinusoidal clock with offset is used to operate the circuit. Simulations verify that the operating frequency can go beyond 70 GHz, with operating margins exceeding 20%. Preliminary measurements indicate that the circuit operates as intended.>

DOI
10.1109/20.92417

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A Josephson SFQ (single flux quantum) shift register circuit operating under a two-phase power was designed and tested. The test cell was fabricated using the Nb/AlO/sub x//Nb junction SNEAP process. The main data latch is DC biased; the data storage is accomplished by the transfer of a single flux quantum in or out of a SQUID (superconducting quantum interference device) superconducting loop. A two-phase sinusoidal clock with offset is used to operate the circuit. Simulations verify that the operating frequency can go beyond 70 GHz, with operating margins exceeding 20%. Preliminary measurements indicate that the circuit operates as intended.>
Testing on a single-flux-quantum (SFQ) shift register fabricated with a SFQ Nb-AlO/sub x/Nb Josephson junction process indicates that a stable flux quantum can be stored in a rapid SFQ (RSFQ) shift register stage and be shifted by SFQ pulses. Design simulations showed that logic errors can occur in SFQ shift registers even though the circuit passes the average voltage test. Three-junction-per-stage shift registers had an advantage over the two-junction-per-stage shift register in handling data with successive 1's and in incorporating resistors to increase tolerance of trapped magnetic flux. Input and output buffers for data and clock pulses were added to get an RSFQ shift register to obtain correct performance. The highest error-free operation speed for the data with successive 1's is about half of the speed for propagation of a lone data 1. Error-free operation of SFQ shift registers with three junctions per stage could be obtained up to speeds of 30-60 GHz with Josephson junctions having I/sub c/R/sub n/ (critical-current-normal-resistance product) values of 600 mu V.>
Some basic cells in the rapid single-flux quantum (RSFQ) family of superconductive logic circuits were studied. An input stage, a buffer, and an OR gate were simulated and laid out for a standard niobium-based fabrication process. The resulting circuits perform properly for clock speeds up to 1 GHz. For the simpler circuits tested, the measured margins are wide, consistent with simulations, and not very dependent on clock speed. However, margin decreases with increased circuit complexity. The input stage converts a rising edge into an SFQ pulse, which has a small amplitude and narrow width in time. On the present circuits, these pulses are about 200 mu V in amplitude and 10 ps in width. To facilitate measurement, the authors have chosen as the output an asymmetrical superconducting quantum interference device (SQUID) consisting of two Josephson junctions. It converts SFQ pulses into 2.5 mV latching output levels on chip. By inductively coupling SFQ pulses into the SQUID loop, DC current isolation between the RSFQ circuit-under-test and the output stage is provided. The SQUID was optimized for 2 GHz operations.>
Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO/sub /x/Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The power dissipation per bit is 3 mu W.>
A 3 bit single flux quantum (SFQ) shift register based on high-Tc bicrystal Josephson junctions has been designed, fabricated, and experimentally tested. The circuit consists of 26 bicrystal Josephson junctions and includes the shift register itself, two dc-SFQ converters, one readout superconducting quantum interference device, serving as a SFQ-dc converter, and three Josephson transmission lines. The correct operation of all circuit components has been demonstrated by low frequency testing at a temperature of 50 K.