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IEEE Transactions on Applied Superconductivity

A 512-bit shift register using compact two-phase single flux quantum clock generators with large margins and low power

Perng-Fei Yuh

Published Jan 1, 1993• 2 citations
Publisher

Abstract

A 512-b shift register was built and tested up to 14.5 GHz. The shift register uses a two-phase clock which is generated by coupling a master control line over many asymmetrically biased two-junction SQUIDs. Compared with other shift registers with Josephson transmission lines to deliver clock, this new clock system provides short delay, low power dissipation, and large DC bias margins. The shift register uses about 3000 Nb/AlO/sub x//Nb Josephson junctions and consumes about 0.1 mW.>

DOI
10.1109/77.251814

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A 512-b shift register was built and tested up to 14.5 GHz. The shift register uses a two-phase clock which is generated by coupling a master control line over many asymmetrically biased two-junction SQUIDs. Compared with other shift registers with Josephson transmission lines to deliver clock, this new clock system provides short delay, low power dissipation, and large DC bias margins. The shift register uses about 3000 Nb/AlO/sub x//Nb Josephson junctions and consumes about 0.1 mW.>
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A two-phase clocking scheme for rapid single flux quantum logic circuits, in particular, shift registers and correlators, is discussed. The two-phase pulse clock is generated on chip with one external clock line. The use of a two-phase clock improves the clock operating margins and eliminate the racethrough problem. A 32-b shift register has been built and tested up to a clock frequency of 21.6 GHz. A one-bit digital correlator with 32 stages has also been tested at low speed. The chips are fabricated using a Nb process.>