© 2026 Aqora Quantum S.A.S.

Terms Privacy Legal Notice

IEEE Transactions on Magnetics

A multichip superconducting microcomputer ETL-JC1

S. Takada, Hiroshi Nakagawa, I. Kurosawa, Masahiro Aoyagi, S. Kosaka, Yoichi Okada, Yoichi Hamazaki

Published Mar 1, 1991• 24 citations

Abstract

A multichip 4-b superconducting microcomputer named ETL-JC1 has been designed based on Josephson LSI technology in order to demonstrate the feasibility of a Josephson computer system. The ETL-JC1 is the first Josephson computer than can execute a computer program stored in the ROM chip. In order to make the ETL-JC1, the following key technologies were developed: an Nb tunnel junction integration process, an LSI logic circuit, memory chips of 1-kb ROM and 1-kb RAM a CAD (computer-aided design) system to develop Josephson LSIs, and a multiphase power supply system. The computer consists of four Josephson LSI chips essential to execute the computer functions of arithmetic-logic, sequence control, program memory, and data memory. The whole computer system was based on a RISC (reduced-instruction-set computer) architecture. The four chips were fabricated using a 3- mu m Nb/Al-oxide/Nb junction integration process. Photomasks for the logic circuits were made by using the CAD system, in which the layout of logic gates on the chip and wiring among them were carried out using a standard-cell method. The 128-step program was executed fully in the ETL-JC1 to test a full set of 27 kinds of basic RISC instructions, memory access, subroutine call/return, and so forth, which are sufficient to make any computer program. The total power dissipation was 6.2 mW in all circuits of the ETL-JC1 consisting of more than 22000 junctions. An operation speed of 1 GIPS (giga-instruction per second) can be expected with single CPU in this system by computer logic simulation.

DOI: 10.1109/20.133749

Related papers

A 1-GHz-clock Josephson microcomputer system

S. Yano, Y. Hatano, H. Mori +4 more

A 1-GHz-clock Josephson microcomputer system was developed to demonstrate the possibility of a high-speed superconducting computer system. It consists of a 4-b data processor chip and a 1-kb RAM chip. For the fabrication of these Josephson integrated circuits, a cross-shaped Nb-AlO/sub x/-Nb Josephson junction process was developed in order to realize small junction size and improve critical current uniformity, and has made fabrication of LSIs with several thousand gates possible. A latchup-free DC flip-flop is an important element in the high-speed Josephson logic and memory circuits, having been applied to an all-DC-powered Josephson RAM with asynchronous access capability. A low-inductance chip-to-chip carrier is an architectural and design concept for the Josephson computer's 1-GHz-clock operation, suppressing the crosstalk between the AC power and the output signals. Each chip is 7 mm square and is fabricated using a 2.5- mu m-rule Nb-AlO/sub x/-Nb junction process. The chips are connected on a superconducting carrier by solder bumps in a die size of 15 mm by 25 mm. The system is constructed from 8123 Josephson interferometer devices and is operable in a 1-ns cycle with 50-mW power dissipation.

IEEE Transactions on Magnetics•Mar 1, 1991•16 citations

Superconductor Wiring in Multichip Module for Josephson LSI Circuits

Shigeo Tanahashi, Takanori Kubo, Kazuhiro Kawabata +7 more

Nb/polyimide stacked layers on a multilayer ceramic substrate makes it possible to fabricate superconducting off-chip wiring for control signal lines. This superconducting multichip module (SuperMCM) also provides matching circuits for the clock signal and DC bias circuits beneath the superconducting transmission lines. The first prototype SuperMCM in the world successfully made,which has been designed to drive Josephson LSI chips at the highest clock frequency of 1.2 GHz.

Japanese Journal of Applied Physics•Jul 1, 1993•12 citations

ARCHITECTURE AND DESIGN OF AN 8-BIT FLUX-1 SUPERCONDUCTOR RSFQ MICROPROCESSOR

M. Dorojevets

The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.

International Journal of High Speed Electronics and Systems•Jun 1, 2002•8 citations

Josephson-CMOS Hybrid Memories

Qingguo Liu, Qingguo Liu

Abstract : Lack of high-density, fast and memory has been a long-standing problem in superconducting digital electronics. Alternative Josephson-junction-based memory cells and peripheral circuits have intrinsic problems which impede the application of that kind of memory. The CMOS-Josephson hybrid memory idea was proposed in 1992 to circumvent this problem. In the present work we have designed and demonstrated a 64-kb CMOS-Josephson hybrid memory working at 1 GHz. In order to make the hybrid idea practical, a complete and comprehensive 4 K short-channel CMOS model for digital circuits was developed for this dissertation. It has been used in the design of the memory core and peripheral circuits. A fast hybrid interface circuit that transforms single-flux-quantum millivolt 2-ps pulse signals to CMOS volt-level signals has been studied and the optimized design has been completed. Using a nonvolatile cryogenic 3-T DRAM cell, the memory core is designed in such a way that the access time is much less than for room-temperature operation, not only because of the performance upgrade due to the temperature decrease but also because of a different reading mechanism. Fabricated by commercial submicron CMOS processes (0.25 microns and 0.18 microns) and a Nb/AlOx/Nb Josephson-junction process with 2.5 kA/cm2 tunneling current density, the memory chips were bonded together by direct wire-bonding and by flip-chip bump-bonding and tested at low frequencies, high frequencies, respectively. A subnanosecond access time is obtained both from simulations and experiments. The power for an interface circuit is measured to be 0.6 mW. The memory core consumes even less power. The total power consumption depends on the operation mode of the memory and is calculated to be 10 mW for reading and 28 mW for writing. Simulations also indicate that, with more advanced semiconductor and superconductor technologies, larger and faster hybrid memories are expected to be achievable in the future.

•Nov 7, 2013•4 citations

Design of an 8-bit Bit-Parallel RSFQ Microprocessor

Pei-Yao Qu, Guang-Ming Tang, Jia-Hong Yang +4 more

With Moore's law approaching its physical limits, low-temperature computing technology is ushering in unprecedented development opportunities. Rapid single-flux-quantum (RSFQ) circuit technology is currently the most mature superconducting integrated circuit technology. Based on the current fabrication process, we propose an 8-bit bit-parallel RSFQ microprocessor. The proposed microprocessor processes 8-bit data each clock cycle. Ten different instructions are executed. The microprocessor mainly consists of an on-chip instruction memory, two data registers, an instruction decoder, an 8-bit bit-parallel arithmetic logic unit, and a program counter. The microprocessor contains 7702 JJs (based on the Open Dataset of CONNECT Cell Library for AIST ADP2) without considering splitters, Josephson transmission lines, and passive transmission lines. We perform a logic-level simulation of the proposed microprocessor. The simulation results show correct operation with a target frequency of 16.7 GHz.

IEEE Transactions on Applied Superconductivity•Aug 18, 2020•12 citations

Toward the Realization of a Josephson Computer

S. Hasuo

High-quality Josephson junctions, with both electrodes made from niobium and with an aluminum-oxide insulating barrier, were introduced in 1983. This niobium junction is very stable, reliable, controllable, and reproducible. Because of these excellent characteristics, these junctions can be applied to large-scale integrated (LSI) circuits, such as microprocessors having a few thousand gates and a few kilobits of memory. These circuits operate much faster and consume less power than any semiconductor circuit now available. Integrated Josephson circuits are now being tested in a closed-cycle refrigerator. The next step is to design a special-purpose, small-scale Josephson computer and to demonstrate its high performance.

Science•Jan 17, 1992•11 citations

A multichip 4-b superconducting microcomputer named ETL-JC1 has been designed based on Josephson LSI technology in order to demonstrate the feasibility of a Josephson computer system. The ETL-JC1 is the first Josephson computer than can execute a computer program stored in the ROM chip. In order to make the ETL-JC1, the following key technologies were developed: an Nb tunnel junction integration process, an LSI logic circuit, memory chips of 1-kb ROM and 1-kb RAM a CAD (computer-aided design) system to develop Josephson LSIs, and a multiphase power supply system. The computer consists of four Josephson LSI chips essential to execute the computer functions of arithmetic-logic, sequence control, program memory, and data memory. The whole computer system was based on a RISC (reduced-instruction-set computer) architecture. The four chips were fabricated using a 3- mu m Nb/Al-oxide/Nb junction integration process. Photomasks for the logic circuits were made by using the CAD system, in which the layout of logic gates on the chip and wiring among them were carried out using a standard-cell method. The 128-step program was executed fully in the ETL-JC1 to test a full set of 27 kinds of basic RISC instructions, memory access, subroutine call/return, and so forth, which are sufficient to make any computer program. The total power dissipation was 6.2 mW in all circuits of the ETL-JC1 consisting of more than 22000 junctions. An operation speed of 1 GIPS (giga-instruction per second) can be expected with single CPU in this system by computer logic simulation.

A 1-GHz-clock Josephson microcomputer system was developed to demonstrate the possibility of a high-speed superconducting computer system. It consists of a 4-b data processor chip and a 1-kb RAM chip. For the fabrication of these Josephson integrated circuits, a cross-shaped Nb-AlO/sub x/-Nb Josephson junction process was developed in order to realize small junction size and improve critical current uniformity, and has made fabrication of LSIs with several thousand gates possible. A latchup-free DC flip-flop is an important element in the high-speed Josephson logic and memory circuits, having been applied to an all-DC-powered Josephson RAM with asynchronous access capability. A low-inductance chip-to-chip carrier is an architectural and design concept for the Josephson computer's 1-GHz-clock operation, suppressing the crosstalk between the AC power and the output signals. Each chip is 7 mm square and is fabricated using a 2.5- mu m-rule Nb-AlO/sub x/-Nb junction process. The chips are connected on a superconducting carrier by solder bumps in a die size of 15 mm by 25 mm. The system is constructed from 8123 Josephson interferometer devices and is operable in a 1-ns cycle with 50-mW power dissipation.

The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.

Abstract : Lack of high-density, fast and memory has been a long-standing problem in superconducting digital electronics. Alternative Josephson-junction-based memory cells and peripheral circuits have intrinsic problems which impede the application of that kind of memory. The CMOS-Josephson hybrid memory idea was proposed in 1992 to circumvent this problem. In the present work we have designed and demonstrated a 64-kb CMOS-Josephson hybrid memory working at 1 GHz. In order to make the hybrid idea practical, a complete and comprehensive 4 K short-channel CMOS model for digital circuits was developed for this dissertation. It has been used in the design of the memory core and peripheral circuits. A fast hybrid interface circuit that transforms single-flux-quantum millivolt 2-ps pulse signals to CMOS volt-level signals has been studied and the optimized design has been completed. Using a nonvolatile cryogenic 3-T DRAM cell, the memory core is designed in such a way that the access time is much less than for room-temperature operation, not only because of the performance upgrade due to the temperature decrease but also because of a different reading mechanism. Fabricated by commercial submicron CMOS processes (0.25 microns and 0.18 microns) and a Nb/AlOx/Nb Josephson-junction process with 2.5 kA/cm2 tunneling current density, the memory chips were bonded together by direct wire-bonding and by flip-chip bump-bonding and tested at low frequencies, high frequencies, respectively. A subnanosecond access time is obtained both from simulations and experiments. The power for an interface circuit is measured to be 0.6 mW. The memory core consumes even less power. The total power consumption depends on the operation mode of the memory and is calculated to be 10 mW for reading and 28 mW for writing. Simulations also indicate that, with more advanced semiconductor and superconductor technologies, larger and faster hybrid memories are expected to be achievable in the future.

With Moore's law approaching its physical limits, low-temperature computing technology is ushering in unprecedented development opportunities. Rapid single-flux-quantum (RSFQ) circuit technology is currently the most mature superconducting integrated circuit technology. Based on the current fabrication process, we propose an 8-bit bit-parallel RSFQ microprocessor. The proposed microprocessor processes 8-bit data each clock cycle. Ten different instructions are executed. The microprocessor mainly consists of an on-chip instruction memory, two data registers, an instruction decoder, an 8-bit bit-parallel arithmetic logic unit, and a program counter. The microprocessor contains 7702 JJs (based on the Open Dataset of CONNECT Cell Library for AIST ADP2) without considering splitters, Josephson transmission lines, and passive transmission lines. We perform a logic-level simulation of the proposed microprocessor. The simulation results show correct operation with a target frequency of 16.7 GHz.

High-quality Josephson junctions, with both electrodes made from niobium and with an aluminum-oxide insulating barrier, were introduced in 1983. This niobium junction is very stable, reliable, controllable, and reproducible. Because of these excellent characteristics, these junctions can be applied to large-scale integrated (LSI) circuits, such as microprocessors having a few thousand gates and a few kilobits of memory. These circuits operate much faster and consume less power than any semiconductor circuit now available. Integrated Josephson circuits are now being tested in a closed-cycle refrigerator. The next step is to design a special-purpose, small-scale Josephson computer and to demonstrate its high performance.