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Japanese Journal of Applied Physics

Superconductor Wiring in Multichip Module for Josephson LSI Circuits

Shigeo Tanahashi, Takanori Kubo, Kazuhiro Kawabata, Ryouji Jikuhara, Gentaro Kaji, Masami Terasawa, Hiroshi Nakagawa, Masahiro Aoyagi, I. Kurosawa, S. Takada

Published Jul 1, 1993• 12 citations
Publisher

Abstract

Nb/polyimide stacked layers on a multilayer ceramic substrate makes it possible to fabricate superconducting off-chip wiring for control signal lines. This superconducting multichip module (SuperMCM) also provides matching circuits for the clock signal and DC bias circuits beneath the superconducting transmission lines. The first prototype SuperMCM in the world successfully made,which has been designed to drive Josephson LSI chips at the highest clock frequency of 1.2 GHz.

DOI
10.1143/jjap.32.l898

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arXiv:1206.6120•Superconductor Science and Technology•Aug 30, 2012•31 citations
Nb/polyimide stacked layers on a multilayer ceramic substrate makes it possible to fabricate superconducting off-chip wiring for control signal lines. This superconducting multichip module (SuperMCM) also provides matching circuits for the clock signal and DC bias circuits beneath the superconducting transmission lines. The first prototype SuperMCM in the world successfully made,which has been designed to drive Josephson LSI chips at the highest clock frequency of 1.2 GHz.
A multichip 4-b superconducting microcomputer named ETL-JC1 has been designed based on Josephson LSI technology in order to demonstrate the feasibility of a Josephson computer system. The ETL-JC1 is the first Josephson computer than can execute a computer program stored in the ROM chip. In order to make the ETL-JC1, the following key technologies were developed: an Nb tunnel junction integration process, an LSI logic circuit, memory chips of 1-kb ROM and 1-kb RAM a CAD (computer-aided design) system to develop Josephson LSIs, and a multiphase power supply system. The computer consists of four Josephson LSI chips essential to execute the computer functions of arithmetic-logic, sequence control, program memory, and data memory. The whole computer system was based on a RISC (reduced-instruction-set computer) architecture. The four chips were fabricated using a 3- mu m Nb/Al-oxide/Nb junction integration process. Photomasks for the logic circuits were made by using the CAD system, in which the layout of logic gates on the chip and wiring among them were carried out using a standard-cell method. The 128-step program was executed fully in the ETL-JC1 to test a full set of 27 kinds of basic RISC instructions, memory access, subroutine call/return, and so forth, which are sufficient to make any computer program. The total power dissipation was 6.2 mW in all circuits of the ETL-JC1 consisting of more than 22000 junctions. An operation speed of 1 GIPS (giga-instruction per second) can be expected with single CPU in this system by computer logic simulation.
A 1-GHz-clock Josephson microcomputer system was developed to demonstrate the possibility of a high-speed superconducting computer system. It consists of a 4-b data processor chip and a 1-kb RAM chip. For the fabrication of these Josephson integrated circuits, a cross-shaped Nb-AlO/sub x/-Nb Josephson junction process was developed in order to realize small junction size and improve critical current uniformity, and has made fabrication of LSIs with several thousand gates possible. A latchup-free DC flip-flop is an important element in the high-speed Josephson logic and memory circuits, having been applied to an all-DC-powered Josephson RAM with asynchronous access capability. A low-inductance chip-to-chip carrier is an architectural and design concept for the Josephson computer's 1-GHz-clock operation, suppressing the crosstalk between the AC power and the output signals. Each chip is 7 mm square and is fabricated using a 2.5- mu m-rule Nb-AlO/sub x/-Nb junction process. The chips are connected on a superconducting carrier by solder bumps in a die size of 15 mm by 25 mm. The system is constructed from 8123 Josephson interferometer devices and is operable in a 1-ns cycle with 50-mW power dissipation.
Integrated circuit chips were designed and fabricated, based on a Josephson shift register circuit that simulated operation at 25 GHz using the SPICE program. The 6.25-mm/sup 2/ chip featured a twelve-gate, four-stage shift register fabricated with Nb/AlO/sub x//Nb Josephson junctions with a design value of 2000 A/cm/sup 2/ critical current density. SUPERCOMPACT, a general program for the design of monolithic microwave integrated circuits, was used to model the effects of layout geometry on the uniformity and phase coherence of logic gate bias currents. A layout geometry for the superconductive transmission lines and thin-film bias resistors was developed. The original SPICE-designed circuit was modified as a result of these calculations. Modeling indicated that bias current variations could be limited to 3% for all possible logic states of the shift register, and phase coherence of the gates could be maintained to within 2 degrees at 10 GHz. The fundamental soundness of the circuit design was demonstrated by the proper operation of fabricated shift registers.>
Digital circuits have been developed to interface superconductive electronic chips with high speed 50-/spl Omega/ transmission lines. Digital data at 1 Gigabit per second was transferred through a Josephson chip in a first cryostat to another Josephson chip in a second cryostat. The chips were connected by more than 3 meters of 50-/spl Omega/ transmission line. No semiconductor amplifiers were used in this data path. A Hewlett Packard data source provided the original data to the first chip, which converted it to SFQ data. Output interface circuits were driven by a 2-GHz external clock to latch series strings of 10 junctions and drive 2-Gbps data into a 50-/spl Omega/ cable. In the second cryostat, a latching three-junction interferometer with a two-turn control line converted the input signal to latched data and switched an MVTL OR-gate output. This demonstration showed that low-power Josephson digital circuits can be integrated into multichip digital subsystems that can pass data at high rates without the use of power-hungry semiconductor amplifiers.
To confirm a gigahertz frequency power supply in a multichip system, three-stage superconductive filter-type powering device (SFPD) chips and a resistive load chip for a 500 gate Josephson device were designed and fabricated. Low-loss capacitors required for this gigahertz operation were also developed. The authors tested the operation of the three-stage SFPDs in a multichip configuration with resistive load. A superconductive power supply with frequencies as high as 2.0 GHz was demonstrated in a multichip system for the first time. For a 2.0-GHz SFPD, normal operation was confirmed with a resonant frequency of 2.1 GHz, a resonant level of -31 dB, and a current gain of 22.4. The 0.1- Omega input impedance of the device system was successfully transformed to 49.9 Omega .>
Superconducting single flux quantum (SFQ) circuits can process information at extremely high speeds, in the range of hundreds of GHz. SFQ circuits are based on Josephson junction cells for switching logic and ballistic transmission for transferring SFQ pulses. Multi-chip modules (MCMs) are often used to implement larger complex designs, which cannot be fit onto a single chip. We have optimized the design of wideband interconnects for transferring signals and SFQ pulses between chips in flip-chip MCMs and evaluated the importance of several design parameters such as the geometry of bump pads on chips, length of passive microstrip lines (MSLs) and number of corners in MSLs as well as flux trapping and fabrication effects on the operating margins of the MCMs. Several test circuits have been designed to evaluate the above mentioned features and fabricated in the framework of a 4.5 kA cm −2 HYPRES process. The MCM bumps for electrical connections have been deposited using a wafer-level electroplating process. We have found that, at the optimized configuration, the maximum operating frequency of the MCM test circuit, a ring oscillator with chip-to-chip connections, approaches 100 GHz and is not noticeably affected by the presence of MCM interconnects, decreasing by only about 3% with respect to the same circuit with no inter-chip connections.