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arXiv:1206.6120 · Superconductor Science and Technology

Design and testing of high-speed interconnects for superconducting multi-chip modules

S Narayana, V K Semenov, Y A Polyakov, V Dotsenko, Sergey K. Tolpygo

Published Aug 30, 2012• 31 citations
arXivHTMLPDF

Abstract

Superconducting single flux quantum (SFQ) circuits can process information at extremely high speeds, in the range of hundreds of GHz. SFQ circuits are based on Josephson junction cells for switching logic and ballistic transmission for transferring SFQ pulses. Multi-chip modules (MCMs) are often used to implement larger complex designs, which cannot be fit onto a single chip. We have optimized the design of wideband interconnects for transferring signals and SFQ pulses between chips in flip-chip MCMs and evaluated the importance of several design parameters such as the geometry of bump pads on chips, length of passive microstrip lines (MSLs) and number of corners in MSLs as well as flux trapping and fabrication effects on the operating margins of the MCMs. Several test circuits have been designed to evaluate the above mentioned features and fabricated in the framework of a 4.5 kA cm −2 HYPRES process. The MCM bumps for electrical connections have been deposited using a wafer-level electroplating process. We have found that, at the optimized configuration, the maximum operating frequency of the MCM test circuit, a ring oscillator with chip-to-chip connections, approaches 100 GHz and is not noticeably affected by the presence of MCM interconnects, decreasing by only about 3% with respect to the same circuit with no inter-chip connections.

DOI
10.1088/0953-2048/25/10/105012

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Superconducting single flux quantum (SFQ) circuits can process information at extremely high speeds, in the range of hundreds of GHz. SFQ circuits are based on Josephson junction cells for switching logic and ballistic transmission for transferring SFQ pulses. Multi-chip modules (MCMs) are often used to implement larger complex designs, which cannot be fit onto a single chip. We have optimized the design of wideband interconnects for transferring signals and SFQ pulses between chips in flip-chip MCMs and evaluated the importance of several design parameters such as the geometry of bump pads on chips, length of passive microstrip lines (MSLs) and number of corners in MSLs as well as flux trapping and fabrication effects on the operating margins of the MCMs. Several test circuits have been designed to evaluate the above mentioned features and fabricated in the framework of a 4.5 kA cm −2 HYPRES process. The MCM bumps for electrical connections have been deposited using a wafer-level electroplating process. We have found that, at the optimized configuration, the maximum operating frequency of the MCM test circuit, a ring oscillator with chip-to-chip connections, approaches 100 GHz and is not noticeably affected by the presence of MCM interconnects, decreasing by only about 3% with respect to the same circuit with no inter-chip connections.
This paper presents the results of theoretical optimization of the multi-chip-module (MCM) contact and driver circuitries for gigabit chip-to-chip communication. Optimization has been done using 3D electromagnetic (EM) simulations of MCM contacts and time domain simulations of drivers and receivers. A single optimized MCM contact has a signal reflection of less than −20 dB for more than 400 GHz bandwidth. The MCM data link with the optimized SFQ driver, receiver and two MCM contacts has operational margins on the global bias current of ± 30% at 30 Gbit s −1 speedand can operate above 100 Gbit s −1 speed. Wide bandwidth transmission requires the realization of an advanced flip–chip process with a small dimension of the MCM contact (less than 30 µm diameter of the contact pad) and small height of the flip–chip contact bumps of the order of 2 µm. Current processes with about 7 µm height of the bumps require the application of a double-flux-quantum (DFQ) driver. The data link with the DFQ driver was also simulated. It has operational margins on the global bias current of ± 30% at 30 Gbit s −1 ; however, the maximum speed of operation is 61 Gbit s −1 . Several test structures have been designed for measurements of signal reflection, bit error rate and operational margins of the data link.
We report experimental results on chip-to-chip transfer of single-flux-quantum (SFQ) pulses using an active multichip module (MCM). Josephson transmitters and receivers are integrated on both a chip and an MCM substrate. An MCM consisting of a 4.8-mm chip and an 8.2-mm MCM substrate was fabricated using a 1.6-kA/cm/sup 2/ Nb-trilayer process and a solder-bumped flip-chip bonding technology. The correct operation of the circuit was confirmed by low-speed testing. Bit-error rate (BER) of the circuit was measured down to 10/sup -5/, and extrapolation of the error-function fits suggested a very small BER, lower than 10/sup -200/, at the optimum bias point. Experimental margins on the bias voltage were as large as /spl plusmn/34%.
We have developed an interchip data transmission scheme through passive transmission lines on a multi-chip-module (MCM) carrier and 100-/spl mu/m solder bump bonds. In rapid single flux quantum (RSFQ) logic, digital data are in the form of single flux quantum (SFQ) pulses. A reliable scheme for transmission of SFQ pulses through non-superconducting solder bumps between chips through a passive MCM substrate is yet to be established. Therefore, we have devised a scheme that converts SFQ pulses into toggles in a voltage waveform for interchip transmission. Data in the form of SFQ pulses are reconstructed from this voltage waveform using a sensitive quantizing pulse receiver. Our objective is to eliminate the need for amplification of the transmitted signal. This is achieved by increasing the receiver sensitivity. However, a sensitive receiver, a dc SQUID, may produce more than one SFQ pulse for each rising/falling edge of the voltage waveform. A simple circuit, pulse resurrection logic (PRL), is employed to discard any extra SFQ pulses. Together with the sensitive quantizer, the PRL circuit makes our scheme error tolerant. We have demonstrated the receiver operation using 3-/spl mu/m Nb RSFQ circuits at frequencies up to 20 GHz.
We developed a multi-chip module (MCM) system of superconducting quantum bits with single-flux quantum (SFQ) interface circuits. The MCM system consists of chips with quantum bits and chips with SFQ circuits mounted on a base chip by flip-chip bonding (FCB) with superconducting solder. We report on a reliability test of the MCM system. The test was done using a resistance measurement of an MCM with 30 mum diameter bumps. Tested samples showed good durability against thermal cycles between room temperature and 4.2 K. At 4.2 K, the resistance measured through more than two hundred bumps in a series was less than 1 mOmega. Along with achieving a high reliability, reducing thermal interference from SFQ circuits to quantum bits is important. We must understand the thermal conductance between and within the chips to design a system with minimum interference. An MCM on-chip thermometer which is based on the Johnson noise thermometry, has been designed and fabricated to achieve this desired level. The preliminary results of the thermal measurement are reported.
Chip-to-chip propagation of a single flux quantum (SFQ) pulse has been demonstrated using an active multichip module (MCM) technique in which active transmitters and receivers are integrated on an MCM substrate as well as on a chip. A chip-to-chip SFQ transfer circuit has been designed and implemented by a standard Nb-trilayer process and solder-bumped flip-chip technology. The correct operation of the circuit has been confirmed by low-frequency testing. Experimental margins for the global factor for bias currents have been as large as /spl plusmn/33%.
Superconducting single flux quantum (SFQ) technology is well known for digital logic operations below 4.2 K, which are compatible with the Josephson junction qubit. Operation speed and signal sensitivity of circuits in SFQ are also sufficient to control qubits. Therefore, the SFQ circuit is a candidate technology for multiple qubit control. However, the self-heating effect of the SFQ circuit is a potential barrier to development of an SFQ-supported multiple qubit system because the qubit operating temperature is lower than the conventional 4.2 K. The multi-chip approach is a possible solution because the qubit chip can be thermally isolated from the SFQ circuitry. We report on recent progress in SFQ circuit and packaging technology for operation at sub-Kelvin temperatures. As for multi-chip module technology, a test sample of the multi-chip module shows good reliability of electrical connections between chips, and each solder bump has a bandwidth wide enough for signal transmission. We have designed lower power SFQ circuits for sub-Kelvin temperatures. The critical currents of Josephson junctions were scaled down, inductances were scaled up, and bias voltage was reduced to make power consumption lower. Based on our fabrication technology, critical current densities were optimized by considering trade-off relations between fabrication availability and operation speed. We successfully confirmed its correct operations at around 0.35 K. The combination of the multi-chip module and optimized SFQ circuits is very effective way of controlling qubit.