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Superconductor Science and Technology

Optimization of high frequency flip–chip interconnects for digital superconducting circuits

M R Rafique, Henrik Engseth, Anna Kidiyarova-Shevchenko

Published Mar 16, 2006• 7 citations
Publisher

Abstract

This paper presents the results of theoretical optimization of the multi-chip-module (MCM) contact and driver circuitries for gigabit chip-to-chip communication. Optimization has been done using 3D electromagnetic (EM) simulations of MCM contacts and time domain simulations of drivers and receivers. A single optimized MCM contact has a signal reflection of less than −20 dB for more than 400 GHz bandwidth. The MCM data link with the optimized SFQ driver, receiver and two MCM contacts has operational margins on the global bias current of ± 30% at 30 Gbit s −1 speedand can operate above 100 Gbit s −1 speed. Wide bandwidth transmission requires the realization of an advanced flip–chip process with a small dimension of the MCM contact (less than 30 µm diameter of the contact pad) and small height of the flip–chip contact bumps of the order of 2 µm. Current processes with about 7 µm height of the bumps require the application of a double-flux-quantum (DFQ) driver. The data link with the DFQ driver was also simulated. It has operational margins on the global bias current of ± 30% at 30 Gbit s −1 ; however, the maximum speed of operation is 61 Gbit s −1 . Several test structures have been designed for measurements of signal reflection, bit error rate and operational margins of the data link.

DOI
10.1088/0953-2048/19/5/s40

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This paper presents the results of theoretical optimization of the multi-chip-module (MCM) contact and driver circuitries for gigabit chip-to-chip communication. Optimization has been done using 3D electromagnetic (EM) simulations of MCM contacts and time domain simulations of drivers and receivers. A single optimized MCM contact has a signal reflection of less than −20 dB for more than 400 GHz bandwidth. The MCM data link with the optimized SFQ driver, receiver and two MCM contacts has operational margins on the global bias current of ± 30% at 30 Gbit s −1 speedand can operate above 100 Gbit s −1 speed. Wide bandwidth transmission requires the realization of an advanced flip–chip process with a small dimension of the MCM contact (less than 30 µm diameter of the contact pad) and small height of the flip–chip contact bumps of the order of 2 µm. Current processes with about 7 µm height of the bumps require the application of a double-flux-quantum (DFQ) driver. The data link with the DFQ driver was also simulated. It has operational margins on the global bias current of ± 30% at 30 Gbit s −1 ; however, the maximum speed of operation is 61 Gbit s −1 . Several test structures have been designed for measurements of signal reflection, bit error rate and operational margins of the data link.
Superconducting single flux quantum (SFQ) circuits can process information at extremely high speeds, in the range of hundreds of GHz. SFQ circuits are based on Josephson junction cells for switching logic and ballistic transmission for transferring SFQ pulses. Multi-chip modules (MCMs) are often used to implement larger complex designs, which cannot be fit onto a single chip. We have optimized the design of wideband interconnects for transferring signals and SFQ pulses between chips in flip-chip MCMs and evaluated the importance of several design parameters such as the geometry of bump pads on chips, length of passive microstrip lines (MSLs) and number of corners in MSLs as well as flux trapping and fabrication effects on the operating margins of the MCMs. Several test circuits have been designed to evaluate the above mentioned features and fabricated in the framework of a 4.5 kA cm −2 HYPRES process. The MCM bumps for electrical connections have been deposited using a wafer-level electroplating process. We have found that, at the optimized configuration, the maximum operating frequency of the MCM test circuit, a ring oscillator with chip-to-chip connections, approaches 100 GHz and is not noticeably affected by the presence of MCM interconnects, decreasing by only about 3% with respect to the same circuit with no inter-chip connections.
Superconducting digital RSFQ technology offers unique digital processing solutions for the telecommunication that allows more than three times increasing capacity of the 3G networks, makes telecommunication receivers reconfigurable and adjustable for different services, and significantly enhances security level of the data transfer over the fibers.Key features of RSFQ technology are high speed, low power and high integration density. In the current international semiconductor roadmap, RSFQ technology is listed as the least risky emerging digital technology. Over two years, the integration density of the RSFQ circuits has been increased more than twice reaching the limit of 12000 active elements per chip. The highest demonstrated clock frequency for large circuits is 60~GHz. The conventional benchmark of a static digital divider is on the limit of 360~GHz frequency. RSFQ design allows full use of commercial CAD tools and supports normal design flows with digital time/delay optimization and complete verification. RSFQ technology also gains a lot from Multi-Chip-Module (MCM) packaging. The lossless superconducting passive interconnects allow implementation of a high speed System-in-Chip (SiP). Record figures with up to 100~Gbit/s transmission for chip-to-chip communication have recently been demonstrated in the USA and Japan.The goal of the research presented in this thesis is to simulate, optimize and design of the superconducting passive interconnects for high integration density RSFQ circuits and superconducting MCM SiP. The novelty of the results is in accurate simulation of the impedance discontinuities that allowed to reduce coupling and return losses for bandwidth of 300~GHz below -20~dB limit and derivation of the general relation between passive interconnects design and fabrication process parameters.The thesis covers all required topics: models of the superconductors for electromagnetic frequency domain simulations, extraction of the equivalent circuits for time-domain simulations, optimization of the general passive structures for on-chip and inter-chip MCM high speed data links, design of the drivers and receivers for matching with active circuits, design of the high voltage driver for communication with room temperature electronics and high speed experimental verification.
Superconductor digital devices using single-flux-quantum (SFQ) data encoding offer higher speed at lower power than any other integrated circuit technology. For this very reason, interconnect is challenging. We report SFQ data transfer between chips flip chip mounted on a passive microstrip carrier. The flip-chip structure achieves bandwidths greater than 250 GHz. Unlike previous designs, our signal lines are terminated at both ends; this is accomplished using a driver that produces a double-flux-quantum signal. We measured the circuit for pseudorandom data in the range of 10–60 Gb/s. Bit error rates are measured down to 1E−10 and extrapolate to negligible values. The signal power on the microstrip is only 30 nW at 60 Gb ps.
We report a demonstration of single-flux-quantum (SFQ) pulse transmission between superconductor chips at throughputs beyond 100 Gbps. A fabrication process with a high junction critical current density of 10kA∕cm2 was used to increase the operation speed of a pulse driver and receiver. The chips were flip-chip bonded on a passive microstrip carrier using small solder bumps with diameters of 30μm. With experiments based on a ring-shaped circuit, chip-to-chip SFQ pulse transmission has been demonstrated up to 117 Gbps with an error rate of less than 10−15. The power dissipated by the driver and receiver was only 0.24μW at 117 Gbps.
Single-flux-quantum (SFQ) pulse transmission between superconductor chips mounted on a passive microstrip carrier is reported. In contrast to the earlier work based on a double-flux-quantum (DFQ) driver, we used an SFQ driver; that is, the simplest driver. To deal with transmission loss at solder-bump bonds, we improved the receiver’s sensitivity by reducing its critical current, and optimized the SFQ driver to have as large an output amplitude as possible with a sufficient bias margin. Chip-to-chip transmission on a passive microstrip carrier with 50μm solder-bump bonds up to 60Gbps has been achieved at a junction critical current density of 2.5KA∕cm2.
We have developed an interchip data transmission scheme through passive transmission lines on a multi-chip-module (MCM) carrier and 100-/spl mu/m solder bump bonds. In rapid single flux quantum (RSFQ) logic, digital data are in the form of single flux quantum (SFQ) pulses. A reliable scheme for transmission of SFQ pulses through non-superconducting solder bumps between chips through a passive MCM substrate is yet to be established. Therefore, we have devised a scheme that converts SFQ pulses into toggles in a voltage waveform for interchip transmission. Data in the form of SFQ pulses are reconstructed from this voltage waveform using a sensitive quantizing pulse receiver. Our objective is to eliminate the need for amplification of the transmitted signal. This is achieved by increasing the receiver sensitivity. However, a sensitive receiver, a dc SQUID, may produce more than one SFQ pulse for each rising/falling edge of the voltage waveform. A simple circuit, pulse resurrection logic (PRL), is employed to discard any extra SFQ pulses. Together with the sensitive quantizer, the PRL circuit makes our scheme error tolerant. We have demonstrated the receiver operation using 3-/spl mu/m Nb RSFQ circuits at frequencies up to 20 GHz.