Superconducting digital RSFQ technology offers unique digital processing solutions for the telecommunication that allows more than three times increasing capacity of the 3G networks, makes telecommunication receivers reconfigurable and adjustable for different services, and significantly enhances security level of the data transfer over the fibers.Key features of RSFQ technology are high speed, low power and high integration density. In the current international semiconductor roadmap, RSFQ technology is listed as the least risky emerging digital technology. Over two years, the integration density of the RSFQ circuits has been increased more than twice reaching the limit of 12000 active elements per chip. The highest demonstrated clock frequency for large circuits is 60~GHz. The conventional benchmark of a static digital divider is on the limit of 360~GHz frequency. RSFQ design allows full use of commercial CAD tools and supports normal design flows with digital time/delay optimization and complete verification. RSFQ technology also gains a lot from Multi-Chip-Module (MCM) packaging. The lossless superconducting passive interconnects allow implementation of a high speed System-in-Chip (SiP). Record figures with up to 100~Gbit/s transmission for chip-to-chip communication have recently been demonstrated in the USA and Japan.The goal of the research presented in this thesis is to simulate, optimize and design of the superconducting passive interconnects for high integration density RSFQ circuits and superconducting MCM SiP. The novelty of the results is in accurate simulation of the impedance discontinuities that allowed to reduce coupling and return losses for bandwidth of 300~GHz below -20~dB limit and derivation of the general relation between passive interconnects design and fabrication process parameters.The thesis covers all required topics: models of the superconductors for electromagnetic frequency domain simulations, extraction of the equivalent circuits for time-domain simulations, optimization of the general passive structures for on-chip and inter-chip MCM high speed data links, design of the drivers and receivers for matching with active circuits, design of the high voltage driver for communication with room temperature electronics and high speed experimental verification.
Superconducting digital RSFQ technology offers unique digital processing solutions for the telecommunication that allows more than three times increasing capacity of the 3G networks, makes telecommunication receivers reconfigurable and adjustable for different services, and significantly enhances security level of the data transfer over the fibers.Key features of RSFQ technology are high speed, low power and high integration density. In the current international semiconductor roadmap, RSFQ technology is listed as the least risky emerging digital technology. Over two years, the integration density of the RSFQ circuits has been increased more than twice reaching the limit of 12000 active elements per chip. The highest demonstrated clock frequency for large circuits is 60GHz. The conventional benchmark of a static digital divider is on the limit of 360GHz frequency. RSFQ design allows full use of commercial CAD tools and supports normal design flows with digital time/delay optimization and complete verification. RSFQ technology also gains a lot from Multi-Chip-Module (MCM) packaging. The lossless superconducting passive interconnects allow implementation of a high speed System-in-Chip (SiP). Record figures with up to 100Gbit/s transmission for chip-to-chip communication have recently been demonstrated in the USA and Japan.The goal of the research presented in this thesis is to simulate, optimize and design of the superconducting passive interconnects for high integration density RSFQ circuits and superconducting MCM SiP. The novelty of the results is in accurate simulation of the impedance discontinuities that allowed to reduce coupling and return losses for bandwidth of 300GHz below -20~dB limit and derivation of the general relation between passive interconnects design and fabrication process parameters.The thesis covers all required topics: models of the superconductors for electromagnetic frequency domain simulations, extraction of the equivalent circuits for time-domain simulations, optimization of the general passive structures for on-chip and inter-chip MCM high speed data links, design of the drivers and receivers for matching with active circuits, design of the high voltage driver for communication with room temperature electronics and high speed experimental verification.
This paper presents the results of theoretical optimization of the multi-chip-module (MCM) contact and driver circuitries for gigabit chip-to-chip communication. Optimization has been done using 3D electromagnetic (EM) simulations of MCM contacts and time domain simulations of drivers and receivers. A single optimized MCM contact has a signal reflection of less than −20 dB for more than 400 GHz bandwidth. The MCM data link with the optimized SFQ driver, receiver and two MCM contacts has operational margins on the global bias current of ± 30% at 30 Gbit s −1 speedand can operate above 100 Gbit s −1 speed. Wide bandwidth transmission requires the realization of an advanced flip–chip process with a small dimension of the MCM contact (less than 30 µm diameter of the contact pad) and small height of the flip–chip contact bumps of the order of 2 µm. Current processes with about 7 µm height of the bumps require the application of a double-flux-quantum (DFQ) driver. The data link with the DFQ driver was also simulated. It has operational margins on the global bias current of ± 30% at 30 Gbit s −1 ; however, the maximum speed of operation is 61 Gbit s −1 . Several test structures have been designed for measurements of signal reflection, bit error rate and operational margins of the data link.
Superconducting single flux quantum (SFQ) circuits can process information at extremely high speeds, in the range of hundreds of GHz. SFQ circuits are based on Josephson junction cells for switching logic and ballistic transmission for transferring SFQ pulses. Multi-chip modules (MCMs) are often used to implement larger complex designs, which cannot be fit onto a single chip. We have optimized the design of wideband interconnects for transferring signals and SFQ pulses between chips in flip-chip MCMs and evaluated the importance of several design parameters such as the geometry of bump pads on chips, length of passive microstrip lines (MSLs) and number of corners in MSLs as well as flux trapping and fabrication effects on the operating margins of the MCMs. Several test circuits have been designed to evaluate the above mentioned features and fabricated in the framework of a 4.5 kA cm −2 HYPRES process. The MCM bumps for electrical connections have been deposited using a wafer-level electroplating process. We have found that, at the optimized configuration, the maximum operating frequency of the MCM test circuit, a ring oscillator with chip-to-chip connections, approaches 100 GHz and is not noticeably affected by the presence of MCM interconnects, decreasing by only about 3% with respect to the same circuit with no inter-chip connections.
Superconducting digital technology based on Rapid Single Flux Quantum logic (RSFQ) is a digital technology characterized by high speed, low power consumption and low operational temperatures. RSFQ is attractive for many applications and in particular for high frequency Digital Signal Processing (DSP) and for digital control of mK devices like superconducting qubits. Due to the 30 GHz clock speed, RSFQ DSP could be used to implement a Successive Interference Canceller for multi-user detection in a 3G wireless systems. The being developed DSP consists of a digital core, an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory and external semiconductor memory.The first part of this thesis is focusing on architecture and implementation of the hierarchical CMOS-RSFQ hybrid memory for the RSFQ DSP. The architecture ofthe RSFQ cache is optimized in order to reach the highest speed and reliable data communication with CMOS memory. Aspects of block synchronization betweenthe RSFQ cache and the RSFQ digital core are discussed and solved using a new developed RSFQ gate, C3. For design of different components of the DSP, a designapproach based on validated VHDL models is proposed and experimentally verified.The second part of this thesis is focusing on the design oflow-dissipative RSFQ circuits for interface to the superconducting qubits. Power dissipation ofRSFQ circuits is minimized. A low-temperature thermal model of resistively shunted Josephsonjunctions is developed and applied to optimize the shape of the shunt resistors in order to reduce their electron temperature. Depending on the available fabricationprocess the lowest noise temperature of RSFQ circuit can be in the range from 90 mK to 180 mK.
Superconductive electronics offers a unique combination of high bandwidth and low power for mission critical hardware such as digital processors at 20 to 100 GHz, microwatt per bit analog to digital converters, large digital switches at multi-Gb/s data rates, and low noise parametric amplifiers. This cryogenic technology, typically operating at a few degrees or a few tens of degrees Kelvin, depends upon the unique physics of superconducting materials such as Nb, NbN, and YBaCuO, and the fundamental circuit element, the Josephson junction (JJ) to create unique architectures of unprecedented design efficiency and performance. These circuits are based on the single flux quantum (SFQ) logic family, a technology that has no parallel in semiconductor electronics. Digital data is transmitted by voltage pulses with amplitude less than 1 mV, but at extremely high speeds. Individual gates have been operated as high as 370 GHz. In this paper, we present a brief overview of superconductive digital technology, describe some recent circuits, and discuss how the challenges to superconductive technology are being met, including the use of multi-chip module (MCM) technology, and the potential use of III-V HBT and HEMT circuits to provide interface drivers and amplifiers, possibly operated cryogenically.
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
AbstractSuperconducting digital technology based on Rapid Single Flux Quantum (RSFQ) logic offers a 50 times faster clock rate and 100 times less on chip power consumption than today's mainstream semiconductor electronics. This technology is attractive for many applications and in particular for Digital Signal Processing (DSP). The applications of the RSFQ DSPs are numerous and include multi-user detection in spread spectrum system, channel equalization for Multi-in, Multi-out (MIMO) systems, and blind detection and signal tracking for signal intelligence.At Chalmers we are developing a hybrid DSP with target performance of 30 giga operations per second. It consists of an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory, and an external semiconductor memory. The development of the complex high speed cryogenic digital system requires interface, packaging and testing solutions. The main difficulties are due to the 4 K operational temperature, the high magnetic field sensitivity of the RSFQ circuits, the multi-channel high bandwidth interface required in the hybrid architecture, and the high speed RSFQ digital core. The key steps towards addressing each of these problems are the subject of this thesis. The main emphasis is put on the experimental testing and interfacing of superconductor electronics. A large part of the work is connected to the experimental verification of DSP components and their incremental improvement towards functionality. The RSFQ circuits tested were fabricated using the four-metal layer VLSI processes available from NGST(8 kA/cm^2 Josephson junction critical current) and HYPRES (both 1 kA/cm^2 and HYPRES 4.5 kA/cm^2. The main results of the work are demonstrations of the RSFQ cache memory with more than 2,000 Josephson junctions, 33.5 GHz operation of the digital clock controller, and 20.48 GHz operation of the autocorrelator. In addition, various experiments have been done for investigation of parasitic effects in RSFQ circuits such as flux trapping and influence of the high current bias lines.At the final stage of the work, a unique high bandwidth 4 K cryocooler based experimental setup has been developed. The system, developed in close cooperation with Hypres Inc. USA, has 40 high speed I/Os with bandwidth of 2 Gbps, 64 DC bias channels, 4 high frequency clock lines, and 4 auxiliary control lines. It supports exchangeable test units for 10 mm x 10 mm and 20 mm x 20 mm Multi Chip Module (MCM) carriers. The availability of such a system is critical to demonstration of the hybrid DSP prototype and future commercialization.