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IEEE Transactions on Applied Superconductivity

Superconductive gigahertz power supply for Josephson multichip systems

Takashi Inoue, Shuichi Tahara, Shuichi Nagasawa, H. Tsuge, Ichiro Ishida

Published Mar 1, 1992• 2 citations
Publisher

Abstract

To confirm a gigahertz frequency power supply in a multichip system, three-stage superconductive filter-type powering device (SFPD) chips and a resistive load chip for a 500 gate Josephson device were designed and fabricated. Low-loss capacitors required for this gigahertz operation were also developed. The authors tested the operation of the three-stage SFPDs in a multichip configuration with resistive load. A superconductive power supply with frequencies as high as 2.0 GHz was demonstrated in a multichip system for the first time. For a 2.0-GHz SFPD, normal operation was confirmed with a resonant frequency of 2.1 GHz, a resonant level of -31 dB, and a current gain of 22.4. The 0.1- Omega input impedance of the device system was successfully transformed to 49.9 Omega .>

DOI
10.1109/77.124923

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Josephson latching logic gates require an ac power supply for correct operation. Owing to the difficulty in fabricating Josephson regulators for large power currents, multi-phase sinusoidal power supply is the preferred method for multi-gigahertz operation. However, the inherently variable ac power reduces device margin for covering process variations. As a result, there exists a strong relationship between circuit size, maximum operating frequency and circuit throughput for a given available margin. The trade-offs between these performance criteria are analyzed for 3-junction-interferometer-based logic gates. Experimental evaluation of the multi-gigahertz operation of small circuits showed that careful design of power supply networks that reduce power supply fluctuations will be needed to maximize performance. Simulation and experimental results are discussed.
A submillimeter wave source based on a new design using Josephson junction arrays has been developed and tested. The maximum rf power, delivered to a 68Ω load and detected on chip, was 47 μW at 394 GHz. Significant power was detected at a number of frequencies from 300 to 500 GHz where the power was 10 μW. The observed power at the designed operating frequency near 400 GHz is consistent with all 500 junctions in the series biased array delivering current in phase to the loads. This is in agreement with simulations of smaller arrays of the same design. The linewidth, inferred from the measured resistance at the point of maximum power, with T=4.2 K, is less than 1 MHz. The minimum inferred linewidth near 400 GHz, at somewhat lower power, is about 100 kHz.
Josephson latching logic gates require an ac power supply for correct operation. Owing to difficulty in fabricating Josephson regulators for large power currents, multi-phase sinusoidal power supply is the preferred method for multi-gigahertz operation. However, the inherently variable ac power reduces device margin for covering process variations. As a result, there exists a strong relationship between circuit size, maximum operating frequency and circuit throughput for a given available margin. The trade-offs between these performance criteria are analyzed for 3-junction-interferometer- based logic gates. Experimental evaluation of the multi- gigahertz operation of small circuits showed that careful design of power supply networks that reduce power supply fluctuations will be needed to maximize performance. Simulation and experimental results will be discussed.
Digital circuits have been developed to interface superconductive electronic chips with high speed 50-/spl Omega/ transmission lines. Digital data at 1 Gigabit per second was transferred through a Josephson chip in a first cryostat to another Josephson chip in a second cryostat. The chips were connected by more than 3 meters of 50-/spl Omega/ transmission line. No semiconductor amplifiers were used in this data path. A Hewlett Packard data source provided the original data to the first chip, which converted it to SFQ data. Output interface circuits were driven by a 2-GHz external clock to latch series strings of 10 junctions and drive 2-Gbps data into a 50-/spl Omega/ cable. In the second cryostat, a latching three-junction interferometer with a two-turn control line converted the input signal to latched data and switched an MVTL OR-gate output. This demonstration showed that low-power Josephson digital circuits can be integrated into multichip digital subsystems that can pass data at high rates without the use of power-hungry semiconductor amplifiers.