A superconductive ring-pipelined network system is proposed to improve performance of multi-processor systems, and a prototype chip is designed. A throughput of a data exchange between processor elements limits the effective performance of the multi-processor systems. The features of the superconductive ring-pipelined network system are a high-clock-frequency operation by using high-speed Josephson gates and wide band superconductive transmission lines, and a high-density package because of its low power consumption. These advantages significantly reduce pipeline loss and improve flexibility in data exchange. Therefore, this network system is capable of improving the overall effective performance of multiprocessor systems. The prototype chip consists of three Josephson ring interface circuits and superconductive interconnections positioned in between these interface circuits. There are a total 1,130 gates. The prototype chip is designed to be operated up to a clock frequency of 10 GHz. Therefore, the total system throughput is estimated to be 60 Gbps.>
A superconductive ring-pipelined network system is proposed to improve performance of multi-processor systems, and a prototype chip is designed. A throughput of a data exchange between processor elements limits the effective performance of the multi-processor systems. The features of the superconductive ring-pipelined network system are a high-clock-frequency operation by using high-speed Josephson gates and wide band superconductive transmission lines, and a high-density package because of its low power consumption. These advantages significantly reduce pipeline loss and improve flexibility in data exchange. Therefore, this network system is capable of improving the overall effective performance of multiprocessor systems. The prototype chip consists of three Josephson ring interface circuits and superconductive interconnections positioned in between these interface circuits. There are a total 1,130 gates. The prototype chip is designed to be operated up to a clock frequency of 10 GHz. Therefore, the total system throughput is estimated to be 60 Gbps.>
We report on the first complete system-level demonstration of a superconducting digital communication system. In today's digital computer and communication systems, managing data flow is a major challenge as the systems have to deal with a huge amount of information. A superconductor device may solve this problem. There have been several attempts to make superconducting switching core circuits, but there have been no complete system-level demonstrations. We have built such a system to demonstrate the efficiency of superconducting devices used in a communication system. Our system is focused on parallel processor communication, and consists of PCs as the processor elements at the three nodes, three interface boxes, and a superconductive chip immersed in a 4.2-K cryostat. The interconnection chip operation is essentially packet switching that was designed with a pipeline ring architecture. The interface box consists of parallel-serial converters, serial-parallel converters, a FIFO output buffer, and a level conversion circuit. The network system operates successfully at approximately 100 MHz, and the clock frequency is restricted by the speed of the interface ICs, not by that of the superconductive chip. We also confirmed the 2-GHz operation of the switching chip, and estimate that the total throughput of the system ran be increased to more than 10 Gbps.
Superconducting digital RSFQ technology offers unique digital processing solutions for the telecommunication that allows more than three times increasing capacity of the 3G networks, makes telecommunication receivers reconfigurable and adjustable for different services, and significantly enhances security level of the data transfer over the fibers.Key features of RSFQ technology are high speed, low power and high integration density. In the current international semiconductor roadmap, RSFQ technology is listed as the least risky emerging digital technology. Over two years, the integration density of the RSFQ circuits has been increased more than twice reaching the limit of 12000 active elements per chip. The highest demonstrated clock frequency for large circuits is 60~GHz. The conventional benchmark of a static digital divider is on the limit of 360~GHz frequency. RSFQ design allows full use of commercial CAD tools and supports normal design flows with digital time/delay optimization and complete verification. RSFQ technology also gains a lot from Multi-Chip-Module (MCM) packaging. The lossless superconducting passive interconnects allow implementation of a high speed System-in-Chip (SiP). Record figures with up to 100~Gbit/s transmission for chip-to-chip communication have recently been demonstrated in the USA and Japan.The goal of the research presented in this thesis is to simulate, optimize and design of the superconducting passive interconnects for high integration density RSFQ circuits and superconducting MCM SiP. The novelty of the results is in accurate simulation of the impedance discontinuities that allowed to reduce coupling and return losses for bandwidth of 300~GHz below -20~dB limit and derivation of the general relation between passive interconnects design and fabrication process parameters.The thesis covers all required topics: models of the superconductors for electromagnetic frequency domain simulations, extraction of the equivalent circuits for time-domain simulations, optimization of the general passive structures for on-chip and inter-chip MCM high speed data links, design of the drivers and receivers for matching with active circuits, design of the high voltage driver for communication with room temperature electronics and high speed experimental verification.
Due to power consumption and speed limitations, the development of CMOS-based large-scale integrated circuits has stagnated in the post-Moore era. While superconducting digital integrated circuit is a promising solution due to its low power consumption and latency. However, the lack of large-scale cryogenic storage units prevents most superconducting chips from being deployed in practical applications. To fully utilize the advantages of superconducting chips and successfully apply them in processing large datasets, we propose a novel heterogeneous processor based on CMOS-based circuits and superconducting chips for processing pattern-matching tasks. In our proposed architecture, a novel communication architecture that enables high-speed, reliable communication between 12 GHz superconducting chips and CMOS circuits is proposed. The hardware overhead for high-speed communication in superconducting chips can be minimized by this approach. In addition, the data communication rate of a single channel can reach 12 Gbps. Simultaneously, we present a 12 GHz, large-scale superconducting chip with 6286 Josephson Junctions that can perform 16-bit pattern matching using the SIMIT-Nb03 process. We have successfully applied our proposed heterogeneous processor to the gene sequence alignment. The processor that uses only one superconducting chip has a throughput of 1.5 Gbp/s (billion base pairs per second), whereas a processor with two superconducting chips has 3 Gbp/s.
A 1-GHz-clock Josephson microcomputer system was developed to demonstrate the possibility of a high-speed superconducting computer system. It consists of a 4-b data processor chip and a 1-kb RAM chip. For the fabrication of these Josephson integrated circuits, a cross-shaped Nb-AlO/sub x/-Nb Josephson junction process was developed in order to realize small junction size and improve critical current uniformity, and has made fabrication of LSIs with several thousand gates possible. A latchup-free DC flip-flop is an important element in the high-speed Josephson logic and memory circuits, having been applied to an all-DC-powered Josephson RAM with asynchronous access capability. A low-inductance chip-to-chip carrier is an architectural and design concept for the Josephson computer's 1-GHz-clock operation, suppressing the crosstalk between the AC power and the output signals. Each chip is 7 mm square and is fabricated using a 2.5- mu m-rule Nb-AlO/sub x/-Nb junction process. The chips are connected on a superconducting carrier by solder bumps in a die size of 15 mm by 25 mm. The system is constructed from 8123 Josephson interferometer devices and is operable in a 1-ns cycle with 50-mW power dissipation.
Superconductive electronics offers a unique combination of high bandwidth and low power for mission critical hardware such as digital processors at 20 to 100 GHz, microwatt per bit analog to digital converters, large digital switches at multi-Gb/s data rates, and low noise parametric amplifiers. This cryogenic technology, typically operating at a few degrees or a few tens of degrees Kelvin, depends upon the unique physics of superconducting materials such as Nb, NbN, and YBaCuO, and the fundamental circuit element, the Josephson junction (JJ) to create unique architectures of unprecedented design efficiency and performance. These circuits are based on the single flux quantum (SFQ) logic family, a technology that has no parallel in semiconductor electronics. Digital data is transmitted by voltage pulses with amplitude less than 1 mV, but at extremely high speeds. Individual gates have been operated as high as 370 GHz. In this paper, we present a brief overview of superconductive digital technology, describe some recent circuits, and discuss how the challenges to superconductive technology are being met, including the use of multi-chip module (MCM) technology, and the potential use of III-V HBT and HEMT circuits to provide interface drivers and amplifiers, possibly operated cryogenically.
A critical component for high bandwidth communications links is a digital switch. Desirable features of a digital switch include: high input/output bandwidth, high channel count, scalability, low latency and interchannel skew. Superconductive circuits, with simultaneous high speed and low power advantages (even including the requisite cryocooler) have been applied to a highly scaleable crossbar switch, useful in supercomputer networks, massively parallel processing (MPP), and high data rate telecommunications. We report here on the testing of a 16/spl times/16 switch chip based on the switch chip component of the highly scaleable crossbar system. We have successfully transmitted multi-Gb/s data through this superconducting switch, with packet destination addressing decoded from the header of the data packet. The data are transmitted to a separate superconducting amplifier chip, mounted on a superconducting multi-chip module with the switch. The switch is a crossbar architecture, voltage state design, and operated to beyond 3 Gb/s. The amplifier is a clocked latching stack of Josephson junctions. Output of the amplifier at 6.2 Gb/s is 7.0 mV, which facilitates the interface of the module to its users. BER of the two-chip assembly is 10/sup -9/ or less above 2 Gb/s.