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IEEE Transactions on Applied Superconductivity

System demonstration of a superconducting communication system

Shinichi Yorozu, Y. Hashimoto, Hideaki Numata, Shuichi Nagasawa, Shuichi Tahara

Published Jun 1, 1999• 4 citations
Publisher

Abstract

We report on the first complete system-level demonstration of a superconducting digital communication system. In today's digital computer and communication systems, managing data flow is a major challenge as the systems have to deal with a huge amount of information. A superconductor device may solve this problem. There have been several attempts to make superconducting switching core circuits, but there have been no complete system-level demonstrations. We have built such a system to demonstrate the efficiency of superconducting devices used in a communication system. Our system is focused on parallel processor communication, and consists of PCs as the processor elements at the three nodes, three interface boxes, and a superconductive chip immersed in a 4.2-K cryostat. The interconnection chip operation is essentially packet switching that was designed with a pipeline ring architecture. The interface box consists of parallel-serial converters, serial-parallel converters, a FIFO output buffer, and a level conversion circuit. The network system operates successfully at approximately 100 MHz, and the clock frequency is restricted by the speed of the interface ICs, not by that of the superconductive chip. We also confirmed the 2-GHz operation of the switching chip, and estimate that the total throughput of the system ran be increased to more than 10 Gbps.

DOI
10.1109/77.783654

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We report on the first complete system-level demonstration of a superconducting digital communication system. In today's digital computer and communication systems, managing data flow is a major challenge as the systems have to deal with a huge amount of information. A superconductor device may solve this problem. There have been several attempts to make superconducting switching core circuits, but there have been no complete system-level demonstrations. We have built such a system to demonstrate the efficiency of superconducting devices used in a communication system. Our system is focused on parallel processor communication, and consists of PCs as the processor elements at the three nodes, three interface boxes, and a superconductive chip immersed in a 4.2-K cryostat. The interconnection chip operation is essentially packet switching that was designed with a pipeline ring architecture. The interface box consists of parallel-serial converters, serial-parallel converters, a FIFO output buffer, and a level conversion circuit. The network system operates successfully at approximately 100 MHz, and the clock frequency is restricted by the speed of the interface ICs, not by that of the superconductive chip. We also confirmed the 2-GHz operation of the switching chip, and estimate that the total throughput of the system ran be increased to more than 10 Gbps.
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A critical component for high bandwidth communications links is a digital switch. Desirable features of a digital switch include: high input/output bandwidth, high channel count, scalability, low latency and interchannel skew. Superconductive circuits, with simultaneous high speed and low power advantages (even including the requisite cryocooler) have been applied to a highly scaleable crossbar switch, useful in supercomputer networks, massively parallel processing (MPP), and high data rate telecommunications. We report here on the testing of a 16/spl times/16 switch chip based on the switch chip component of the highly scaleable crossbar system. We have successfully transmitted multi-Gb/s data through this superconducting switch, with packet destination addressing decoded from the header of the data packet. The data are transmitted to a separate superconducting amplifier chip, mounted on a superconducting multi-chip module with the switch. The switch is a crossbar architecture, voltage state design, and operated to beyond 3 Gb/s. The amplifier is a clocked latching stack of Josephson junctions. Output of the amplifier at 6.2 Gb/s is 7.0 mV, which facilitates the interface of the module to its users. BER of the two-chip assembly is 10/sup -9/ or less above 2 Gb/s.
Superconducting digital RSFQ technology offers unique digital processing solutions for the telecommunication that allows more than three times increasing capacity of the 3G networks, makes telecommunication receivers reconfigurable and adjustable for different services, and significantly enhances security level of the data transfer over the fibers.Key features of RSFQ technology are high speed, low power and high integration density. In the current international semiconductor roadmap, RSFQ technology is listed as the least risky emerging digital technology. Over two years, the integration density of the RSFQ circuits has been increased more than twice reaching the limit of 12000 active elements per chip. The highest demonstrated clock frequency for large circuits is 60~GHz. The conventional benchmark of a static digital divider is on the limit of 360~GHz frequency. RSFQ design allows full use of commercial CAD tools and supports normal design flows with digital time/delay optimization and complete verification. RSFQ technology also gains a lot from Multi-Chip-Module (MCM) packaging. The lossless superconducting passive interconnects allow implementation of a high speed System-in-Chip (SiP). Record figures with up to 100~Gbit/s transmission for chip-to-chip communication have recently been demonstrated in the USA and Japan.The goal of the research presented in this thesis is to simulate, optimize and design of the superconducting passive interconnects for high integration density RSFQ circuits and superconducting MCM SiP. The novelty of the results is in accurate simulation of the impedance discontinuities that allowed to reduce coupling and return losses for bandwidth of 300~GHz below -20~dB limit and derivation of the general relation between passive interconnects design and fabrication process parameters.The thesis covers all required topics: models of the superconductors for electromagnetic frequency domain simulations, extraction of the equivalent circuits for time-domain simulations, optimization of the general passive structures for on-chip and inter-chip MCM high speed data links, design of the drivers and receivers for matching with active circuits, design of the high voltage driver for communication with room temperature electronics and high speed experimental verification.
We developed a 4×4 SFQ network switch prototype system and demonstrated its operation at 10Gbps. The system's core is composed of two SFQ chips: a 4×4 switch and a 6-channel voltage driver. The 4×4 switch chip contained both a switch fabric (i. e. a data path) and a switch scheduler (i. e. a controller). Both chips were attached to a multichip-module (MCM) carrier, which was then installed in a cryocooled system with 32 10-Gbps ports. Each chip contained about 2100 Josephson junctions on a 5-mm×5-mm die. An NEC standard 2.5-kA/cm2 fabrication process was used for the switch chip. We increased the critical current density to 10kA/cm2 for the driver chip to improve speed while maintaining wide bias margins. MCM implementation enabled us to use a hybrid critical current density technology. Voltage pulses were transferred between two chips through passive transmission lines on the MCM carrier. The cryocooled system was cooled down to about 4K using a two-stage 1-W cryocooler. We correctly operated the whole system at 10Gbps. The switch scheduler, which is driven by an on-chip clock generator, operated at 40GHz. The speed gap between SFQ and room temperature devices was filled by on-chip SFQ FIFO buffers or shift registers. We measured the bit error rate at 10Gbps and found that it was on the order of 10-13 for the 4×4 SFQ switch fabric. In addition, using semiconductor interface circuitry, we built a four-port SFQ Ethernet switch. All the components except for a compressor were installed in a standard 19-inch rack, filling a space 21 U (933.5mm or 36.75 inches) in height. After four personal computers (PCs) were connected to the switch, we have successfully transferred video data between them.
Digital circuits have been developed to interface superconductive electronic chips with high speed 50-/spl Omega/ transmission lines. Digital data at 1 Gigabit per second was transferred through a Josephson chip in a first cryostat to another Josephson chip in a second cryostat. The chips were connected by more than 3 meters of 50-/spl Omega/ transmission line. No semiconductor amplifiers were used in this data path. A Hewlett Packard data source provided the original data to the first chip, which converted it to SFQ data. Output interface circuits were driven by a 2-GHz external clock to latch series strings of 10 junctions and drive 2-Gbps data into a 50-/spl Omega/ cable. In the second cryostat, a latching three-junction interferometer with a two-turn control line converted the input signal to latched data and switched an MVTL OR-gate output. This demonstration showed that low-power Josephson digital circuits can be integrated into multichip digital subsystems that can pass data at high rates without the use of power-hungry semiconductor amplifiers.
Superconducting devices have intrinsically superior characteristics to those of semiconductor devices. Presently, we can fabricate more than twenty thousand junctions on one chip using niobium technology. We have demonstrated the operation of a network system with a superconducting interconnection chip using voltage-state logic. Single flux quantum devices are promising for future superconducting applications because the clock frequency of SFQ logic is higher than that of voltage-state. We have proposed a high-end switch based on hybrid architecture using optical devices, semiconductors and SFQ devices. To demonstrate the high-speed operation of SFQ circuits, we developed an arbiter circuit that uses SFQ components and the arbiter circuit operates at 60 GHz. We also have developed a high Tc superconducting (HTS) SFQ sampler system for observing ultra-fast signal waveforms. In addition, we will discuss the prospects of future superconducting devices based on the fabrication technologies we developed.