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IEICE Transactions on Electronics

Design and Demonstration of a 4 x4 SFQ Network Switch Prototype System and 10-Gbps Bit-Error-Rate Measurement

Y. KAMEDA, Y. HASHIMOTO, Shinichi Yorozu

Published Mar 1, 2008• 10 citations
Publisher

Abstract

We developed a 4×4 SFQ network switch prototype system and demonstrated its operation at 10Gbps. The system's core is composed of two SFQ chips: a 4×4 switch and a 6-channel voltage driver. The 4×4 switch chip contained both a switch fabric (i. e. a data path) and a switch scheduler (i. e. a controller). Both chips were attached to a multichip-module (MCM) carrier, which was then installed in a cryocooled system with 32 10-Gbps ports. Each chip contained about 2100 Josephson junctions on a 5-mm×5-mm die. An NEC standard 2.5-kA/cm2 fabrication process was used for the switch chip. We increased the critical current density to 10kA/cm2 for the driver chip to improve speed while maintaining wide bias margins. MCM implementation enabled us to use a hybrid critical current density technology. Voltage pulses were transferred between two chips through passive transmission lines on the MCM carrier. The cryocooled system was cooled down to about 4K using a two-stage 1-W cryocooler. We correctly operated the whole system at 10Gbps. The switch scheduler, which is driven by an on-chip clock generator, operated at 40GHz. The speed gap between SFQ and room temperature devices was filled by on-chip SFQ FIFO buffers or shift registers. We measured the bit error rate at 10Gbps and found that it was on the order of 10-13 for the 4×4 SFQ switch fabric. In addition, using semiconductor interface circuitry, we built a four-port SFQ Ethernet switch. All the components except for a compressor were installed in a standard 19-inch rack, filling a space 21 U (933.5mm or 36.75 inches) in height. After four personal computers (PCs) were connected to the switch, we have successfully transferred video data between them.

DOI
10.1093/ietele/e91-c.3.333

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We developed a 4×4 SFQ network switch prototype system and demonstrated its operation at 10Gbps. The system's core is composed of two SFQ chips: a 4×4 switch and a 6-channel voltage driver. The 4×4 switch chip contained both a switch fabric (i. e. a data path) and a switch scheduler (i. e. a controller). Both chips were attached to a multichip-module (MCM) carrier, which was then installed in a cryocooled system with 32 10-Gbps ports. Each chip contained about 2100 Josephson junctions on a 5-mm×5-mm die. An NEC standard 2.5-kA/cm2 fabrication process was used for the switch chip. We increased the critical current density to 10kA/cm2 for the driver chip to improve speed while maintaining wide bias margins. MCM implementation enabled us to use a hybrid critical current density technology. Voltage pulses were transferred between two chips through passive transmission lines on the MCM carrier. The cryocooled system was cooled down to about 4K using a two-stage 1-W cryocooler. We correctly operated the whole system at 10Gbps. The switch scheduler, which is driven by an on-chip clock generator, operated at 40GHz. The speed gap between SFQ and room temperature devices was filled by on-chip SFQ FIFO buffers or shift registers. We measured the bit error rate at 10Gbps and found that it was on the order of 10-13 for the 4×4 SFQ switch fabric. In addition, using semiconductor interface circuitry, we built a four-port SFQ Ethernet switch. All the components except for a compressor were installed in a standard 19-inch rack, filling a space 21 U (933.5mm or 36.75 inches) in height. After four personal computers (PCs) were connected to the switch, we have successfully transferred video data between them.
We report on development of a cryocooled system prototype for high-throughput single flux quantum (SFQ) digital applications. The system was designed to have 32 I/O links with a bandwidth of 10 Gbps/port. An SFQ multi-chip module (MCM), double mu-metal magnetic shields, a 40-K radiation shield, customized GaAs cryogenic amplifiers, a 32-pin wide-bandwidth cryo-probe, and 32 I/O cables were packaged in a vacuum chamber together with a two-stage 4-K 1-W Gifford-McMahon (G-M) cryocooler. S-parameter measurements showed that the analog bandwidth of the I/O link was 23 GHz. We demonstrated high-speed cryocooled operation of a test module, in which a 5 mm times 5 mm SFQ circuit chip was flip-chip bonded on a 16 mm times 16 mm MCM carrier with phi30 mum InSn bump bonds, at bit rates up to 12.5 Gbps. Measured bit error rate (BER) was less than 10-12for a 1023- 1 pseudorandom bit sequence (PRBS) at 10 Gbps.
A cryocooled system with I/O interface circuits, which enables high-speed system operation of superconductive single-flux-quantum (SFQ) circuits at over 40GHz, and the demonstration of a 47-Gbps SFQ 2×2 switch system are presented. The cryocooled system has 32 I/Os and cools an SFQ multi-chip module (MCM) to 4K with a two-stage 1W Gifford-McMahon cryocooler. An SFQ 4:1 multiplexer (MUX) and an SFQ 1:4 demultiplexer (DEMUX) have been designed to interface the speed gap between the I/O (-10Gbps/ch) and SFQ circuits (>40GHz). An SFQ 2×2 switch chip, in which the MUX/DEMUX and an SFQ 2×2 switch are integrated, and an 8-channel superconductive voltage driver (SVD) chip have been designed with an advanced cell library for a junction critical current density of 10kA/cm2. An SFQ 2×2 switch MCM has been made by flip-chip bonding the switch chip and SVD chip on a superconductive MCM carrier with ∅50-μm InSn solder bumps. An SFQ 2×2 switch system, which is the switch MCM packaged in the cryocooled system, has been demonstrated up to a port speed of 47Gbps for the first time.
4/spl times/4 single-flux-quantum (SFQ) network switch has been packaged and successfully demonstrated in a hybrid closed-cycle refrigerator (CCR) system at multigigabit data rates. Full operation of the packaged switch, with self-routing of 1-Gb/s data packets, was demonstrated using a 1-GHz address header decode. The switch is packaged on a superconducting multichip module (MCM) mounted on the 4.5-K stage of the CCR. On-chip asynchronous Josephson drivers and cooled GaAs preamplifiers are used to amplify the SFQ outputs of the switch. The maximum operation bandwidth of the switch is currently limited by the asynchronous Josephson driver. New designs of the Josephson drivers, which have demonstrated operation at 10 Gb/s, are expected to enable switch operation at 10 Gb/s. The system is equipped with fiber-optical inputs and high-speed cryogenic photodetectors. The fiber-optic interfaces, RF packaging, and MCM packaging in the CCR system have demonstrated error-free operation at 10 Gb/s.
We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.
We report a demonstration of single-flux-quantum (SFQ) pulse transmission between superconductor chips at throughputs beyond 100 Gbps. A fabrication process with a high junction critical current density of 10kA∕cm2 was used to increase the operation speed of a pulse driver and receiver. The chips were flip-chip bonded on a passive microstrip carrier using small solder bumps with diameters of 30μm. With experiments based on a ring-shaped circuit, chip-to-chip SFQ pulse transmission has been demonstrated up to 117 Gbps with an error rate of less than 10−15. The power dissipated by the driver and receiver was only 0.24μW at 117 Gbps.
A single-flux-quantum (SFQ) device provides fast operation with low power consumption. As SFQ devices can be applied in network switches requiring high throughput, we have been developing an SFQ network switch system. Not only the switch fabric but also the switch scheduler is a key component for a high-throughput network switch. The switch scheduler orders multiple inputs to a single output at the same time to prevent collisions from occurring in the switch fabric. The scheduling time becomes longer as the number of switch ports increases, because the scheduler must scan requests from all input ports. We designed two types of 4-port arbiters (i.e. switch scheduler sub-circuits) with structures based on serial or parallel processing. We chose to implement and demonstrate the serial arbiter because it has a smaller number of gates. It consisted of about 1800 Josephson junctions, including on-chip test circuitry. We tested a fabricated circuit at high speed and confirmed its correct operation at 40 GHz.