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IEICE Transactions on Electronics

Development of Cryopackaging and I/O Technologies for High-Speed Superconductive Digital Systems

Y. HASHIMOTO, Shinichi Yorozu, Y. KAMEDA

Published Mar 1, 2008• 27 citations
Publisher

Abstract

A cryocooled system with I/O interface circuits, which enables high-speed system operation of superconductive single-flux-quantum (SFQ) circuits at over 40GHz, and the demonstration of a 47-Gbps SFQ 2×2 switch system are presented. The cryocooled system has 32 I/Os and cools an SFQ multi-chip module (MCM) to 4K with a two-stage 1W Gifford-McMahon cryocooler. An SFQ 4:1 multiplexer (MUX) and an SFQ 1:4 demultiplexer (DEMUX) have been designed to interface the speed gap between the I/O (-10Gbps/ch) and SFQ circuits (>40GHz). An SFQ 2×2 switch chip, in which the MUX/DEMUX and an SFQ 2×2 switch are integrated, and an 8-channel superconductive voltage driver (SVD) chip have been designed with an advanced cell library for a junction critical current density of 10kA/cm2. An SFQ 2×2 switch MCM has been made by flip-chip bonding the switch chip and SVD chip on a superconductive MCM carrier with ∅50-μm InSn solder bumps. An SFQ 2×2 switch system, which is the switch MCM packaged in the cryocooled system, has been demonstrated up to a port speed of 47Gbps for the first time.

DOI
10.1093/ietele/e91-c.3.325

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A cryocooled system with I/O interface circuits, which enables high-speed system operation of superconductive single-flux-quantum (SFQ) circuits at over 40GHz, and the demonstration of a 47-Gbps SFQ 2×2 switch system are presented. The cryocooled system has 32 I/Os and cools an SFQ multi-chip module (MCM) to 4K with a two-stage 1W Gifford-McMahon cryocooler. An SFQ 4:1 multiplexer (MUX) and an SFQ 1:4 demultiplexer (DEMUX) have been designed to interface the speed gap between the I/O (-10Gbps/ch) and SFQ circuits (>40GHz). An SFQ 2×2 switch chip, in which the MUX/DEMUX and an SFQ 2×2 switch are integrated, and an 8-channel superconductive voltage driver (SVD) chip have been designed with an advanced cell library for a junction critical current density of 10kA/cm2. An SFQ 2×2 switch MCM has been made by flip-chip bonding the switch chip and SVD chip on a superconductive MCM carrier with ∅50-μm InSn solder bumps. An SFQ 2×2 switch system, which is the switch MCM packaged in the cryocooled system, has been demonstrated up to a port speed of 47Gbps for the first time.
We report on development of a cryocooled system prototype for high-throughput single flux quantum (SFQ) digital applications. The system was designed to have 32 I/O links with a bandwidth of 10 Gbps/port. An SFQ multi-chip module (MCM), double mu-metal magnetic shields, a 40-K radiation shield, customized GaAs cryogenic amplifiers, a 32-pin wide-bandwidth cryo-probe, and 32 I/O cables were packaged in a vacuum chamber together with a two-stage 4-K 1-W Gifford-McMahon (G-M) cryocooler. S-parameter measurements showed that the analog bandwidth of the I/O link was 23 GHz. We demonstrated high-speed cryocooled operation of a test module, in which a 5 mm times 5 mm SFQ circuit chip was flip-chip bonded on a 16 mm times 16 mm MCM carrier with phi30 mum InSn bump bonds, at bit rates up to 12.5 Gbps. Measured bit error rate (BER) was less than 10-12for a 1023- 1 pseudorandom bit sequence (PRBS) at 10 Gbps.
We developed a 4×4 SFQ network switch prototype system and demonstrated its operation at 10Gbps. The system's core is composed of two SFQ chips: a 4×4 switch and a 6-channel voltage driver. The 4×4 switch chip contained both a switch fabric (i. e. a data path) and a switch scheduler (i. e. a controller). Both chips were attached to a multichip-module (MCM) carrier, which was then installed in a cryocooled system with 32 10-Gbps ports. Each chip contained about 2100 Josephson junctions on a 5-mm×5-mm die. An NEC standard 2.5-kA/cm2 fabrication process was used for the switch chip. We increased the critical current density to 10kA/cm2 for the driver chip to improve speed while maintaining wide bias margins. MCM implementation enabled us to use a hybrid critical current density technology. Voltage pulses were transferred between two chips through passive transmission lines on the MCM carrier. The cryocooled system was cooled down to about 4K using a two-stage 1-W cryocooler. We correctly operated the whole system at 10Gbps. The switch scheduler, which is driven by an on-chip clock generator, operated at 40GHz. The speed gap between SFQ and room temperature devices was filled by on-chip SFQ FIFO buffers or shift registers. We measured the bit error rate at 10Gbps and found that it was on the order of 10-13 for the 4×4 SFQ switch fabric. In addition, using semiconductor interface circuitry, we built a four-port SFQ Ethernet switch. All the components except for a compressor were installed in a standard 19-inch rack, filling a space 21 U (933.5mm or 36.75 inches) in height. After four personal computers (PCs) were connected to the switch, we have successfully transferred video data between them.
Superconductive electronics offers a unique combination of high bandwidth and low power for mission critical hardware such as digital processors at 20 to 100 GHz, microwatt per bit analog to digital converters, large digital switches at multi-Gb/s data rates, and low noise parametric amplifiers. This cryogenic technology, typically operating at a few degrees or a few tens of degrees Kelvin, depends upon the unique physics of superconducting materials such as Nb, NbN, and YBaCuO, and the fundamental circuit element, the Josephson junction (JJ) to create unique architectures of unprecedented design efficiency and performance. These circuits are based on the single flux quantum (SFQ) logic family, a technology that has no parallel in semiconductor electronics. Digital data is transmitted by voltage pulses with amplitude less than 1 mV, but at extremely high speeds. Individual gates have been operated as high as 370 GHz. In this paper, we present a brief overview of superconductive digital technology, describe some recent circuits, and discuss how the challenges to superconductive technology are being met, including the use of multi-chip module (MCM) technology, and the potential use of III-V HBT and HEMT circuits to provide interface drivers and amplifiers, possibly operated cryogenically.
A superconductive single flux quantum (SFQ) digital integrated circuit with an optical data input has been demonstrated at the system level of 40 Gbit/s for the first time. A uni travelling carrier photodiode (UTC-PD) and an SFQ circuit chip, on which 40 Gbit/s I/O interfaces were integrated, were packaged on a cold stage (4–6 K) of a cryocooler system. The UTC-PD's output was connected to an input port of the SFQ circuit with a Cu coaxial cable. From room temperature, a 40 GHz clock was supplied to the SFQ circuit while 40 Gbit/s optical data were supplied to the UTC-PD. The SFQ circuit operated correctly with the optical 40 Gbit/s data. The measured bit error rate was less than 10−13 for 1.2 mW optical PRBS 7 input at 40 Gbit/s.
We have developed the fabrication process, the circuit design technology, and the cryopackaging technology for high-Tc single flux quantum (SFQ) devices with the aim of application to an analog-to-digital (A/D) converter circuit for future wireless communication and a sampler system for high-speed measurements. Reproducibility of fabricating rampedge Josephson junctions with IcRn products above 1mV at 40K and small Ic spreads on a superconducting groundplane was much improved by employing smooth multilayer structures and optimizing the junction fabrication process. The separated base-electrode layout (SBL) method that suppresses the Jc spread for interface-modified junctions in circuits was developed. This method enabled low-frequency logic operations of various elementary SFQ circuits with relatively wide bias current margins and operation of a toggle-flip-flop (T-FF) above 200GHz at 40K. Operation of a 1:2 demultiplexer, one of main elements of a hybrid-type Σ-Δ A/D converter circuit, was also demonstrated. We developed a sampler system in which a sampler circuit with a potential bandwidth over 100GHz was cooled by a compact stirling cooler, and waveform observation experiments confirmed the actual system bandwidth well over 50GHz.
4/spl times/4 single-flux-quantum (SFQ) network switch has been packaged and successfully demonstrated in a hybrid closed-cycle refrigerator (CCR) system at multigigabit data rates. Full operation of the packaged switch, with self-routing of 1-Gb/s data packets, was demonstrated using a 1-GHz address header decode. The switch is packaged on a superconducting multichip module (MCM) mounted on the 4.5-K stage of the CCR. On-chip asynchronous Josephson drivers and cooled GaAs preamplifiers are used to amplify the SFQ outputs of the switch. The maximum operation bandwidth of the switch is currently limited by the asynchronous Josephson driver. New designs of the Josephson drivers, which have demonstrated operation at 10 Gb/s, are expected to enable switch operation at 10 Gb/s. The system is equipped with fiber-optical inputs and high-speed cryogenic photodetectors. The fiber-optic interfaces, RF packaging, and MCM packaging in the CCR system have demonstrated error-free operation at 10 Gb/s.