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IEEE Transactions on Applied Superconductivity

Implementation and Experimental Evaluation of a Cryocooled System Prototype for High-Throughput SFQ Digital Applications

Y. Hashimoto, Shinichi Yorozu, Toshiyuki Miyazaki, Y.. Kameda, Hideo Suzuki, Nobuyuki Yoshikawa

Published Jun 1, 2007• 42 citations
Publisher

Abstract

We report on development of a cryocooled system prototype for high-throughput single flux quantum (SFQ) digital applications. The system was designed to have 32 I/O links with a bandwidth of 10 Gbps/port. An SFQ multi-chip module (MCM), double mu-metal magnetic shields, a 40-K radiation shield, customized GaAs cryogenic amplifiers, a 32-pin wide-bandwidth cryo-probe, and 32 I/O cables were packaged in a vacuum chamber together with a two-stage 4-K 1-W Gifford-McMahon (G-M) cryocooler. S-parameter measurements showed that the analog bandwidth of the I/O link was 23 GHz. We demonstrated high-speed cryocooled operation of a test module, in which a 5 mm times 5 mm SFQ circuit chip was flip-chip bonded on a 16 mm times 16 mm MCM carrier with phi30 mum InSn bump bonds, at bit rates up to 12.5 Gbps. Measured bit error rate (BER) was less than 10-12for a 1023- 1 pseudorandom bit sequence (PRBS) at 10 Gbps.

DOI
10.1109/tasc.2007.898126

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We report on development of a cryocooled system prototype for high-throughput single flux quantum (SFQ) digital applications. The system was designed to have 32 I/O links with a bandwidth of 10 Gbps/port. An SFQ multi-chip module (MCM), double mu-metal magnetic shields, a 40-K radiation shield, customized GaAs cryogenic amplifiers, a 32-pin wide-bandwidth cryo-probe, and 32 I/O cables were packaged in a vacuum chamber together with a two-stage 4-K 1-W Gifford-McMahon (G-M) cryocooler. S-parameter measurements showed that the analog bandwidth of the I/O link was 23 GHz. We demonstrated high-speed cryocooled operation of a test module, in which a 5 mm times 5 mm SFQ circuit chip was flip-chip bonded on a 16 mm times 16 mm MCM carrier with phi30 mum InSn bump bonds, at bit rates up to 12.5 Gbps. Measured bit error rate (BER) was less than 10-12for a 1023- 1 pseudorandom bit sequence (PRBS) at 10 Gbps.
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We developed a 4×4 SFQ network switch prototype system and demonstrated its operation at 10Gbps. The system's core is composed of two SFQ chips: a 4×4 switch and a 6-channel voltage driver. The 4×4 switch chip contained both a switch fabric (i. e. a data path) and a switch scheduler (i. e. a controller). Both chips were attached to a multichip-module (MCM) carrier, which was then installed in a cryocooled system with 32 10-Gbps ports. Each chip contained about 2100 Josephson junctions on a 5-mm×5-mm die. An NEC standard 2.5-kA/cm2 fabrication process was used for the switch chip. We increased the critical current density to 10kA/cm2 for the driver chip to improve speed while maintaining wide bias margins. MCM implementation enabled us to use a hybrid critical current density technology. Voltage pulses were transferred between two chips through passive transmission lines on the MCM carrier. The cryocooled system was cooled down to about 4K using a two-stage 1-W cryocooler. We correctly operated the whole system at 10Gbps. The switch scheduler, which is driven by an on-chip clock generator, operated at 40GHz. The speed gap between SFQ and room temperature devices was filled by on-chip SFQ FIFO buffers or shift registers. We measured the bit error rate at 10Gbps and found that it was on the order of 10-13 for the 4×4 SFQ switch fabric. In addition, using semiconductor interface circuitry, we built a four-port SFQ Ethernet switch. All the components except for a compressor were installed in a standard 19-inch rack, filling a space 21 U (933.5mm or 36.75 inches) in height. After four personal computers (PCs) were connected to the switch, we have successfully transferred video data between them.
A superconductive single flux quantum (SFQ) digital integrated circuit with an optical data input has been demonstrated at the system level of 40 Gbit/s for the first time. A uni travelling carrier photodiode (UTC-PD) and an SFQ circuit chip, on which 40 Gbit/s I/O interfaces were integrated, were packaged on a cold stage (4–6 K) of a cryocooler system. The UTC-PD's output was connected to an input port of the SFQ circuit with a Cu coaxial cable. From room temperature, a 40 GHz clock was supplied to the SFQ circuit while 40 Gbit/s optical data were supplied to the UTC-PD. The SFQ circuit operated correctly with the optical 40 Gbit/s data. The measured bit error rate was less than 10−13 for 1.2 mW optical PRBS 7 input at 40 Gbit/s.
We report a demonstration of single-flux-quantum (SFQ) pulse transmission between superconductor chips at throughputs beyond 100 Gbps. A fabrication process with a high junction critical current density of 10kA∕cm2 was used to increase the operation speed of a pulse driver and receiver. The chips were flip-chip bonded on a passive microstrip carrier using small solder bumps with diameters of 30μm. With experiments based on a ring-shaped circuit, chip-to-chip SFQ pulse transmission has been demonstrated up to 117 Gbps with an error rate of less than 10−15. The power dissipated by the driver and receiver was only 0.24μW at 117 Gbps.
We developed a multi-chip module (MCM) system of superconducting quantum bits with single-flux quantum (SFQ) interface circuits. The MCM system consists of chips with quantum bits and chips with SFQ circuits mounted on a base chip by flip-chip bonding (FCB) with superconducting solder. We report on a reliability test of the MCM system. The test was done using a resistance measurement of an MCM with 30 mum diameter bumps. Tested samples showed good durability against thermal cycles between room temperature and 4.2 K. At 4.2 K, the resistance measured through more than two hundred bumps in a series was less than 1 mOmega. Along with achieving a high reliability, reducing thermal interference from SFQ circuits to quantum bits is important. We must understand the thermal conductance between and within the chips to design a system with minimum interference. An MCM on-chip thermometer which is based on the Johnson noise thermometry, has been designed and fabricated to achieve this desired level. The preliminary results of the thermal measurement are reported.
We have designed a fully integrated 5-bit flash-type single-flux quantum (SFQ) analog-to-digital converter (ADC), in which an error correction and a bit-interleaving circuit are integrated with complementary quasi-one-junction SQUID (CQOS) comparators, and we verified its operation in experiments. Two types of look-back error correction circuits with different clock schemes were designed for the integrated ADCs to avoid the gray zone in comparators and to convert gray code to binary code. The interleaving circuit was also used in the ADC to add one extra bit. A binary 5-bit A/D converter was integrated into an IC chip. Then, input waveforms at low frequencies were successfully retrieved from the binary data of the A/D converter without any errors. We also confirmed that the A/D converter operated properly by conducting tests in our cryocooling system using a 4K-GM cryocooler after the chip was flip-chip bonded onto a multi-chip-module (MCM) carrier. We also used the beat frequency method to test and confirm that the CQOS comparator operated effectively at high frequency, i.e., 3 bits at 15 GHz in the binary code operation and 4 bits at 15 GHz in the gray code operation. Furthermore, operations at sampling frequencies of up to 32 and 50 GHz with a low-frequency analog input signal were experimentally confirmed for a 4-bit comparator circuit with a critical current density Jcof 2.5 kA/cm2and 10 kA/cm2, respectively.