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IEEE Transactions on Applied Superconductivity

Design and Demonstration of a 5-Bit Flash-Type SFQ A/D Converter Integrated With Error Correction and Interleaving Circuits

Hideo Suzuki, M. Oikawa, K. Nishii, Kiyoshi Ishihara, K. Fujiwara, Michitaka Maruyama, M. Hidaka

Published Dec 22, 2010• 15 citations
Publisher

Abstract

We have designed a fully integrated 5-bit flash-type single-flux quantum (SFQ) analog-to-digital converter (ADC), in which an error correction and a bit-interleaving circuit are integrated with complementary quasi-one-junction SQUID (CQOS) comparators, and we verified its operation in experiments. Two types of look-back error correction circuits with different clock schemes were designed for the integrated ADCs to avoid the gray zone in comparators and to convert gray code to binary code. The interleaving circuit was also used in the ADC to add one extra bit. A binary 5-bit A/D converter was integrated into an IC chip. Then, input waveforms at low frequencies were successfully retrieved from the binary data of the A/D converter without any errors. We also confirmed that the A/D converter operated properly by conducting tests in our cryocooling system using a 4K-GM cryocooler after the chip was flip-chip bonded onto a multi-chip-module (MCM) carrier. We also used the beat frequency method to test and confirm that the CQOS comparator operated effectively at high frequency, i.e., 3 bits at 15 GHz in the binary code operation and 4 bits at 15 GHz in the gray code operation. Furthermore, operations at sampling frequencies of up to 32 and 50 GHz with a low-frequency analog input signal were experimentally confirmed for a 4-bit comparator circuit with a critical current density Jcof 2.5 kA/cm2and 10 kA/cm2, respectively.

DOI
10.1109/tasc.2010.2091933

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Investigation of a 5-bit Flash-Type SFQ A/D Converter Using 10 kA/cm2\hbox{kA/cm}^{2}kA/cm2 Niobium Process and Locally Isolated Grounds
We have investigated technologies for high-frequency and stable operation in a 5-bit flash-type single-flux quantum analog-to-digital (A/D) converter. We designed and evaluated several comparators with different designs of the transformer and found that the length of the primary line was the principal factor to determine the bandwidth, which was improved from 7 to 13 GHz by reducing the length from 860 to 290 μm. We have also investigated methods to avoid incorrect operation caused by ground return current of the bias current: one is locally extracting the return current around the component circuits, and the other is to use locally isolated ground for each component circuit. An integrated 5-bit A/D converter with an error correction circuit was designed using the locally isolated ground structure, which can avoid ground return current inflow from other component circuits. The A/D converter was operated without extracting ground return current and 10 GHz operation was carried out by means of the beat frequency method in our cryocooling system. Operation for an optical input signal was also observed. In addition, 100 GHz sampling clock operation with 1 kHz input signal was confirmed.
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This paper presents the progress we have made on our design, fabrication, and testing of a fully parallel superconducting analog-to-digital converter (ADC) with multi-GHz clock frequencies and input bandwidth. To our best knowledge, this converter is the first flash-type analog-to-digital converter ever reported in Josephson technology that fully integrates a quantizer and a thermometer-to-binary encoder to achieve binary outputs. In this design, the quantizer consists of 2(superscript N-1 comparators, each of which is realized using a hysteretic one- junction sampling SQUID driving a two-junction readout SQUID. A new logic family has been designed based on the same comparator building block and has been used to implement the thermometer-to- binary encoder. Taking advantage of the fact that the encoder's input is thermometer-coded, we have designed three-input and four-input quasi-XOR gates with only three NAND gates and therefore reduced significantly the total gate count. Functionalities of all the sub-circuits have been verified experimentally at clock frequencies up to 3 GHz, which is limited by our currently available testing equipment.
Successful utilization of the quasi one-junction SQUID (QOS) as a signal comparator for analog-to-digital conversion (ADC) has been demonstrated by several groups, This idea is extended to show how similar comparators can be integrated into an all rapid single flux quantum (RSFQ) digital architecture. Comparators are interrogated by SFQ sampling pulses and in turn give output according to the RSFQ convention. One- and two-bit ADC's have been simulated, fabricated and tested at low speed. Total performance of these devices is estimated within the framework of a multiple bit parallel flash ADC architecture.>
The authors report on the high-speed operation of a superconducting comparator circuit, based on coupling the quantum flux parametron (QFP) to an RF SQUID, which can be used to build a flash-type analog-to-digital converter (ADC). Simulations of this circuit show that it is expected to achieve operation with input signal bandwidths greater than 4 GHz and with a dynamic range equal to at least 4 b of resolution. A QFP-based comparator fabricated with a process using NbN/Pb-alloy Josephson junctions of 5 mu m by 5 mu m and a current density of 100 A/cm/sup 2/ has been examined to evaluate the properties of the QFP-ADC. Analog-to-digital conversion of the comparator has been observed with a QFP activation frequency up to 18.2 GHz. By employing a sampling method, input signals with frequencies up to 5.4 GHz have also been digitized.>
We have proposed a multi-bit sigma-delta analog-to-digital converter (ADC) in which a modulator is composed of a single quantizer and multiple samplers based on the single-flux-quantum (SFQ) circuits. The quantizer converts analog signals to pulse-density-modulated signals, and the samplers sample the modulated SFQ pulses in every sampling clock. Use of multiple samplers based on delayed-flip-flops (DFFs) increases sampling frequencies virtually, resulting in a multi-bit sigma-delta modulator. We also designed a decimation filter by using the well-established Verilog tools for the SFQ circuits and the Matlab simulator. We prepared an ADC including 4 samplers and a second-order decimation filter with the decimation rate of 1:256 based on the Nb junction technology. We confirmed correct operation of this ADC at 56 GHz clock signals generated by an internal ring oscillator. We experimentally obtained the signal-to-noise ratio of 25 dB and spurious-free dynamic range of 37 dB at the bandwidth of 10 MHz from the upper 7 bits of the outputs of the decimation filter.