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IEEE Transactions on Applied Superconductivity

Demonstration of the Multi-Bit Sigma-Delta A/D Converter With the Decimation Filter

A. Sekiya, Kenichi Okada, Y. Nishido, Akira Fujimaki, Hisao Hayakawa

Published Jun 1, 2005• 13 citations
Publisher

Abstract

We have proposed a multi-bit sigma-delta analog-to-digital converter (ADC) in which a modulator is composed of a single quantizer and multiple samplers based on the single-flux-quantum (SFQ) circuits. The quantizer converts analog signals to pulse-density-modulated signals, and the samplers sample the modulated SFQ pulses in every sampling clock. Use of multiple samplers based on delayed-flip-flops (DFFs) increases sampling frequencies virtually, resulting in a multi-bit sigma-delta modulator. We also designed a decimation filter by using the well-established Verilog tools for the SFQ circuits and the Matlab simulator. We prepared an ADC including 4 samplers and a second-order decimation filter with the decimation rate of 1:256 based on the Nb junction technology. We confirmed correct operation of this ADC at 56 GHz clock signals generated by an internal ring oscillator. We experimentally obtained the signal-to-noise ratio of 25 dB and spurious-free dynamic range of 37 dB at the bandwidth of 10 MHz from the upper 7 bits of the outputs of the decimation filter.

DOI
10.1109/tasc.2005.849828

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We have proposed a multi-bit sigma-delta analog-to-digital converter (ADC) in which a modulator is composed of a single quantizer and multiple samplers based on the single-flux-quantum (SFQ) circuits. The quantizer converts analog signals to pulse-density-modulated signals, and the samplers sample the modulated SFQ pulses in every sampling clock. Use of multiple samplers based on delayed-flip-flops (DFFs) increases sampling frequencies virtually, resulting in a multi-bit sigma-delta modulator. We also designed a decimation filter by using the well-established Verilog tools for the SFQ circuits and the Matlab simulator. We prepared an ADC including 4 samplers and a second-order decimation filter with the decimation rate of 1:256 based on the Nb junction technology. We confirmed correct operation of this ADC at 56 GHz clock signals generated by an internal ring oscillator. We experimentally obtained the signal-to-noise ratio of 25 dB and spurious-free dynamic range of 37 dB at the bandwidth of 10 MHz from the upper 7 bits of the outputs of the decimation filter.
The sigma-delta architecture is the method of choice for analog-to-digital converters (ADCs) for high dynamic range applications. This architecture uses oversampling and precise feedback to generate a shaped spectral distribution of the quantization noise. Subsequent digital filtering suppresses out-of-band quantization noise, yielding a large signal to in-band noise ratio. A unique advantage of superconducting electronics is the availability of the flux quantum to provide quantum mechanically accurate feedback at GHz rates. Josephson digital technology extends sigma-delta ADCs from MHz sampling rates to GHz sampling rates, from kHz signal bandwidths to MHz signal bandwidths, with comparable or better dynamic range when compared to semiconductor implementations. This paper presents circuits for Josephson sigma-delta ADCs, including single-loop and double-loop modulators operating at sampling rates up to 2 GHz, and circuits for quantized feedback. The first demonstration of double-loop noise shaping is also presented.
Last year we presented the first fully operational superconducting Analog-to-Digital Converter (ADC) with on-chip Digital Signal Processing (DSP). Here we review this device and introduce completed and prospective innovations required to exceed the performance of the best semiconductor counterparts. The ADC chip contains 2 basic parts: a "fundamental" ADC operating at about 20 GHz sampling rate and a digital decimation filter which attenuates high-frequency noise components and reduces the sampling rate to match it with the bandwidth of an input signal. Our short term goal is to achieve 14 bits Spurious Free Dynamic Range (SFDR) for 60 MHz signal bandwidth by using the standard 1000 A/cm/sup 2/ Nb-trilayer fabrication technology commercially available at HYPRES, Inc.
We have successfully fabricated and tested a high temperature superconducting (HTS) sigma-delta modulator for analogue-to-digital conversion. This is the first demonstration of a GHz sampling A-to-D in HTS. The 15-junction single-flux-quantum (SFQ) circuit, fabricated using an epitaxial multilayer HTS process with YBCO/Co-YBCO/YBCO edge junctions, was internally clocked at 27 GHz and used to convert a 5.01 MHz signal. The modulator demonstrated a spur-free dynamic range of more than 75 dB. Two-tone measurements with 5.01 MHz and 5.51 MHz signals demonstrated third-order intermodulation products to be lower than -59 dBc. Demonstration of a functional HTS modulator represents a significant milestone in the development of high dynamic range ADCs suitable for such applications as surveillance radar.
We describe the design of an oversampling single-flux-counting analog-to-digital converter with the estimated bandwidth of a few tens of MHz, based on Rapid Single-Flux-Quantum (RSFQ) devices. It consists of an input analog circuit, high-speed quantizer with an original analog/digital negative feedback loop, decimation (comb) filter, and supporting subsystems including clock distribution circuits, quantization signal conditioner, and output drivers. We have applied a new approach, the 'symmetrizing' negative feedback, to free the quantizer from the intrinsic hysteresis without dynamic range sacrifice. The 16-bit version of the system comprises about 1,500 Josephson junctions and consumes 1.2 mW of DC power, when implemented using Nb-trilayer technology with 1 kA/cm/sup 2/, 3.5 /spl mu/m Josephson junctions. All subsystems of the converter have been successfully tested and testing of the system as a whole is in progress.>
We have designed a fully integrated 5-bit flash-type single-flux quantum (SFQ) analog-to-digital converter (ADC), in which an error correction and a bit-interleaving circuit are integrated with complementary quasi-one-junction SQUID (CQOS) comparators, and we verified its operation in experiments. Two types of look-back error correction circuits with different clock schemes were designed for the integrated ADCs to avoid the gray zone in comparators and to convert gray code to binary code. The interleaving circuit was also used in the ADC to add one extra bit. A binary 5-bit A/D converter was integrated into an IC chip. Then, input waveforms at low frequencies were successfully retrieved from the binary data of the A/D converter without any errors. We also confirmed that the A/D converter operated properly by conducting tests in our cryocooling system using a 4K-GM cryocooler after the chip was flip-chip bonded onto a multi-chip-module (MCM) carrier. We also used the beat frequency method to test and confirm that the CQOS comparator operated effectively at high frequency, i.e., 3 bits at 15 GHz in the binary code operation and 4 bits at 15 GHz in the gray code operation. Furthermore, operations at sampling frequencies of up to 32 and 50 GHz with a low-frequency analog input signal were experimentally confirmed for a 4-bit comparator circuit with a critical current density Jcof 2.5 kA/cm2and 10 kA/cm2, respectively.
We have been developing a superconducting second-order sigma-delta analog-to-digital converter with a large bandwidth and a large dynamic range for software radio applications. In a superconducting second-order sigma-delta modulator utilizing a passive integrator and single-flux-quantum (SFQ) feedback, gain to compensate the large attenuation in the passive integrator of the modulator is required to obtain a large dynamic range. In this paper, a second-order modulator utilizing multi-flux-quantum (MFQ) generators creating the needed gain is reported and the design and experimental test results of the elementary circuits including a comparator, a first-order modulator, and the MFQ generator are described. The digital outputs of the comparator and the first-order modulator were experimentally evaluated, where the input dependence of the comparator switching probability and the noise-shaping properties of the modulator were clearly observed. The low speed operation of the MFQ generator creating three SFQ pulses was experimentally confirmed. The other circuits were also tested at low frequencies.