IEEE Transactions on Applied Superconductivity

Superconducting delta ADC with on-chip decimation filter

Vasili K. Semenov, Y.A. Polyakov, Timur V. Filippov

Published Jun 1, 1999• 26 citations

Abstract

Last year we presented the first fully operational superconducting Analog-to-Digital Converter (ADC) with on-chip Digital Signal Processing (DSP). Here we review this device and introduce completed and prospective innovations required to exceed the performance of the best semiconductor counterparts. The ADC chip contains 2 basic parts: a "fundamental" ADC operating at about 20 GHz sampling rate and a digital decimation filter which attenuates high-frequency noise components and reduces the sampling rate to match it with the bandwidth of an input signal. Our short term goal is to achieve 14 bits Spurious Free Dynamic Range (SFDR) for 60 MHz signal bandwidth by using the standard 1000 A/cm/sup 2/ Nb-trilayer fabrication technology commercially available at HYPRES, Inc.

DOI: 10.1109/77.783666

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