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IEEE Military Communications Conference (MILCOM)

Superconductor analog to digital converter for sigint applications

Amol Inamdar, Deepnarayan Gupta, Timur V. Filippov, I. V. Vernik, Andrei Talalaevskii, Anubhav Sahu, Saad M. Sarwana, Anna Leese de Escobar, Deborah van Vechten

Published Nov 1, 2008• 8 citations
Publisher

Abstract

Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. We report recent advances in the low-pass phase-modulation-demodulation (PMD) oversampled analog-to-digital converter (ADC). The oversampled data from the PMD front-end are passed along with sampling clock to an on-chip digital filter. In the past, the maximum frequency of operation of such chips were limited by that of the digital decimation filter (DDF) to about 30 GHz. Recently, we have designed a chip that allows the PMD front-end to be clocked twice as fast as the DDF, resulting in sampling rates of 46.08 GHz and 29.44 GHz for chips with critical current densities of 4.5 and 1 kA/cm2respectively. We have also designed a new PMD front-end, with a quarter-rate quantizer (QRQ) that allows 18-20 dB extension of dynamic range. We are also pursuing a subranging ADC design with two PMD front-ends connected with fluxon amplifier and subtractor circuitry that promises a dynamic range extension by 25-30 dB. We report signal-to-noise ratio and spur-free dynamic range measurement results for various ADC chips, and project performance for future improvements.

DOI
10.1109/milcom.2008.4753449

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Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. We report recent advances in the low-pass phase-modulation-demodulation (PMD) oversampled analog-to-digital converter (ADC). The oversampled data from the PMD front-end are passed along with sampling clock to an on-chip digital filter. In the past, the maximum frequency of operation of such chips were limited by that of the digital decimation filter (DDF) to about 30 GHz. Recently, we have designed a chip that allows the PMD front-end to be clocked twice as fast as the DDF, resulting in sampling rates of 46.08 GHz and 29.44 GHz for chips with critical current densities of 4.5 and 1 kA/cm2respectively. We have also designed a new PMD front-end, with a quarter-rate quantizer (QRQ) that allows 18-20 dB extension of dynamic range. We are also pursuing a subranging ADC design with two PMD front-ends connected with fluxon amplifier and subtractor circuitry that promises a dynamic range extension by 25-30 dB. We report signal-to-noise ratio and spur-free dynamic range measurement results for various ADC chips, and project performance for future improvements.
We describe the design of a new oversampled analog-to-digital converter (ADC) based on phase modulation-demodulation (PMD) architecture. In a PMD ADC, the analog input signal modulates the phase of a periodic stream of fluxons applied to a modulator circuit for subsequent demodulation in a clocked synchronizer circuit to produce a digital code. The new modulator provides a way to quadruple the average fluxon transport rate, and hence the input dynamic range, by replacing the single junction interferometer with a high-speed symmetric divide-by-4 circuit. The divider acts as a 1:4 asynchronous demultiplexer which distributes incoming fluxons among its four quarter-rate outputs. This four-fold rate reduction, at the modulator output, allows one to increase the ADC maximum input slew rate to 2 fluxons per clock period, achieving 2 additional bits of resolution at the same sampling clock frequency. We have designed and fabricated a quarter-rate ADC front-end and present low frequency test results for the same. The ADC comprises a quarter-rate quantizer which has been successfully tested at an input frequency of 81.92 GHz.
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The sigma-delta architecture is the method of choice for analog-to-digital converters (ADCs) for high dynamic range applications. This architecture uses oversampling and precise feedback to generate a shaped spectral distribution of the quantization noise. Subsequent digital filtering suppresses out-of-band quantization noise, yielding a large signal to in-band noise ratio. A unique advantage of superconducting electronics is the availability of the flux quantum to provide quantum mechanically accurate feedback at GHz rates. Josephson digital technology extends sigma-delta ADCs from MHz sampling rates to GHz sampling rates, from kHz signal bandwidths to MHz signal bandwidths, with comparable or better dynamic range when compared to semiconductor implementations. This paper presents circuits for Josephson sigma-delta ADCs, including single-loop and double-loop modulators operating at sampling rates up to 2 GHz, and circuits for quantized feedback. The first demonstration of double-loop noise shaping is also presented.