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IEEE Transactions on Applied Superconductivity

Superconducting high-resolution A/D converter based on phase modulation and multichannel timing arbitration

Sergey V. Rylov, R. P. Robertazzi

Published Jun 1, 1995• 54 citations
Publisher

Abstract

We have developed a flux-quantizing A/D converter (ADC) based on RSFQ elements, employing a novel front end capable of generating high-linearity multibit differential code within a wide dynamic range (up to 16 bits). The front end operates as a phase modulator/demodulator and uses fractional-flux-quantum least significant bit (LSB). It runs at multi-GHz speed, enabling ADCs with large oversampling ratio and effective resolution in excess of 20 bits (after decimation filtering). We have designed, fabricated and tested several versions of a complete ADC using this new architecture and demonstrated its operation with dynamic range of 14 bits. We have also confirmed continuous phase modulation of the flux quantizer with a carrier frequency of 10 GHz.>

DOI
10.1109/77.403035

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IEEE Transactions on Applied Superconductivity•Mar 1, 2004•10 citations
We have developed a flux-quantizing A/D converter (ADC) based on RSFQ elements, employing a novel front end capable of generating high-linearity multibit differential code within a wide dynamic range (up to 16 bits). The front end operates as a phase modulator/demodulator and uses fractional-flux-quantum least significant bit (LSB). It runs at multi-GHz speed, enabling ADCs with large oversampling ratio and effective resolution in excess of 20 bits (after decimation filtering). We have designed, fabricated and tested several versions of a complete ADC using this new architecture and demonstrated its operation with dynamic range of 14 bits. We have also confirmed continuous phase modulation of the flux quantizer with a carrier frequency of 10 GHz.>
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Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. We report recent advances in the low-pass phase-modulation-demodulation (PMD) oversampled analog-to-digital converter (ADC). The oversampled data from the PMD front-end are passed along with sampling clock to an on-chip digital filter. In the past, the maximum frequency of operation of such chips were limited by that of the digital decimation filter (DDF) to about 30 GHz. Recently, we have designed a chip that allows the PMD front-end to be clocked twice as fast as the DDF, resulting in sampling rates of 46.08 GHz and 29.44 GHz for chips with critical current densities of 4.5 and 1 kA/cm2respectively. We have also designed a new PMD front-end, with a quarter-rate quantizer (QRQ) that allows 18-20 dB extension of dynamic range. We are also pursuing a subranging ADC design with two PMD front-ends connected with fluxon amplifier and subtractor circuitry that promises a dynamic range extension by 25-30 dB. We report signal-to-noise ratio and spur-free dynamic range measurement results for various ADC chips, and project performance for future improvements.
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