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IEEE Transactions on Applied Superconductivity

High resolution ADC system

Sergey V. Rylov, Lewis A. Bunz, Dmitri V. Gaidarenko, Michael A. Fisher, R. P. Robertazzi, Oleg A. Mukhanov

Published Jun 1, 1997• 25 citations
Publisher

Abstract

We have developed and verified experimentally a novel high-resolution superconducting ADC architecture based on phase modulation/demodulation principle and implemented in RSFQ logic. We have demonstrated an ADC chip providing full implementation of this architecture, including on-chip decimation filter and multiple-channel synchronizer. We have also developed a digital ADC evaluation system consisting of an interface electronics block converting the low-voltage ADC output to standard TTL form at multi-MHz sampling rate, and a computerized test station performing data acquisition, processing and display in real time. Using this system we have demonstrated that for low-frequency (kHz) signals our ADC chips possess linearity in excess of 16 bits with Spur-Free Dynamic Range over 108 dB, which is an important benchmark for any high-resolution ADC technology.

DOI
10.1109/77.621783

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We have developed and verified experimentally a novel high-resolution superconducting ADC architecture based on phase modulation/demodulation principle and implemented in RSFQ logic. We have demonstrated an ADC chip providing full implementation of this architecture, including on-chip decimation filter and multiple-channel synchronizer. We have also developed a digital ADC evaluation system consisting of an interface electronics block converting the low-voltage ADC output to standard TTL form at multi-MHz sampling rate, and a computerized test station performing data acquisition, processing and display in real time. Using this system we have demonstrated that for low-frequency (kHz) signals our ADC chips possess linearity in excess of 16 bits with Spur-Free Dynamic Range over 108 dB, which is an important benchmark for any high-resolution ADC technology.
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