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IEEE Transactions on Applied Superconductivity

Design of Front-End Circuit for Superconductive A/D Converter and Demonstration of Operation Up to 43 GHz

Futoshi Furuta, K. Saitoh, Kazumasa Takagi

Published Mar 1, 2004• 10 citations
Publisher

Abstract

We designed a front-end circuit for an analog-to-digital (A/D) converter based on single flux quantum circuitry and tested its functionality at a frequency of up to 43 GHz. The front-end circuit consisted of a pulse generator, a sigma-delta modulator, a 1-to-8 demultiplexer (DEMUX), and superconducting quantum interference device (SQUID) amplifiers. There were 2518 Josephson junctions in the front-end circuit. To operate the circuit at high speed, we designed robust timing against variations in circuit parameters. By using circuit simulations based on the Monte Carlo method, we estimated spread in time lag between clock and data pulses. From this estimate, the timing was optimized to operate the circuit at 40 GHz. The demonstration of the front-end circuit was carried out using the on-chip testing method. Output data were acquired from the modulator through DEMUX. We confirmed proper sigma-delta modulation by analyzing the dependence of the density "1" in the output data on input current level. The proper operation was confirmed in a range of 37-43 GHz. Furthermore, the amplification by the SQUID amplifier was also confirmed at low speed. These results indicate the complete operation of the front-end circuit for superconductive A/D converter.

DOI
10.1109/tasc.2004.824343

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We designed a front-end circuit for an analog-to-digital (A/D) converter based on single flux quantum circuitry and tested its functionality at a frequency of up to 43 GHz. The front-end circuit consisted of a pulse generator, a sigma-delta modulator, a 1-to-8 demultiplexer (DEMUX), and superconducting quantum interference device (SQUID) amplifiers. There were 2518 Josephson junctions in the front-end circuit. To operate the circuit at high speed, we designed robust timing against variations in circuit parameters. By using circuit simulations based on the Monte Carlo method, we estimated spread in time lag between clock and data pulses. From this estimate, the timing was optimized to operate the circuit at 40 GHz. The demonstration of the front-end circuit was carried out using the on-chip testing method. Output data were acquired from the modulator through DEMUX. We confirmed proper sigma-delta modulation by analyzing the dependence of the density "1" in the output data on input current level. The proper operation was confirmed in a range of 37-43 GHz. Furthermore, the amplification by the SQUID amplifier was also confirmed at low speed. These results indicate the complete operation of the front-end circuit for superconductive A/D converter.
We have proposed an improved design of the front-end circuit for superconducting analog-to-digital (A/D) converters. The assumed structure of the A/D converter consists of a front-end circuit based on single flux quantum circuitry and a back-end circuit based on semiconductor circuits. To complete the A/D converter, it is necessary to enable synchronous operation between the front-end circuit and assumed back-end circuit. In the present framework, the front-end circuit consists of a ladder-type pulse generator, a modulator, a hybrid DEMUX, shift-registers and stack-type amplifiers. The voltage level of the output data signal is enlarged to about 10 mV by using stack-type amplifiers. Furthermore, the timing margin for synchronization is improved by using a hybrid demultiplexing method. We also have designed a front-end circuit based on the present framework and verified its functionalities at low speed. It was experimentally confirmed that the timing margin in a 1-to-4 hybrid DEMUX was enlarged to three times as large as in the conventional binary-tree DEMUX. A high-voltage output signal of 11 mV was also obtained. From these results, we conclude that functionalities of the designed front-end circuit are correct.
We designed a superconducting front-end circuit for an analog-to-digital converter and experimentally evaluated its signal-to-noise-ratio (SNR) at a sampling frequency of 10 GHz. The modulator was based on a first-order sigma-delta modulation with an LR integrator. Correct noise shaping was experimentally confirmed, and an SNR of 70.9 dB at a bandwidth of 10 MHz was achieved. In the circuit design, we investigated the effect of leakage in the LR integrator and thermal noise on the SNR by using transfer function analysis and circuit simulations with noise sources. Circuit parameters were designed to keep the discrepancy of the SNR from the ideal value (77.6 dB) within 6 dB. In the experimental evaluation, the modulated data signal from the superconducting chip was accumulated with room-temperature electronics. A fast Fourier transform (FFT) calculation was performed to obtain power spectra and SNRs. The power spectra and SNRs were consistent with the predictions of the transfer function analysis and circuit simulations.
This paper presents a superconducting bandpass /spl Delta//spl Sigma/ modulator for direct analog-to-digital conversion of radio frequency signals in the gigahertz range. The design, based on a 2.23-GHz microstrip resonator and a single flux quantum comparator, exploits several advantages of superconducting electronics: the high quality factor of resonators, the fast switching speed of the Josephson junction, natural quantization of voltage pulses, and high circuit sensitivity. The modulator test chip includes an integrated acquisition memory for capturing output data at sampling rates up to 45 GHz. The small size (256 b) of the acquisition memory limits the frequency resolution of spectra based on standard fast Fourier transforms. Output spectra with enhanced resolution are obtained with a segmented correlation method. At a 42.6-GHz sampling rate, the measured SNR is 49 dB over a 20.8-MHz bandwidth, and a full-scale (FS) input is -17.4 dBm. At a 40.2-GHz sampling rate, the measured in-band noise is -57 dBFS over a 19.6-MHz bandwidth. The modulator test chip contains 4065 Josephson junctions and dissipates 1.9 mW at T=4.2 K.
Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. We report recent advances in the low-pass phase-modulation-demodulation (PMD) oversampled analog-to-digital converter (ADC). The oversampled data from the PMD front-end are passed along with sampling clock to an on-chip digital filter. In the past, the maximum frequency of operation of such chips were limited by that of the digital decimation filter (DDF) to about 30 GHz. Recently, we have designed a chip that allows the PMD front-end to be clocked twice as fast as the DDF, resulting in sampling rates of 46.08 GHz and 29.44 GHz for chips with critical current densities of 4.5 and 1 kA/cm2respectively. We have also designed a new PMD front-end, with a quarter-rate quantizer (QRQ) that allows 18-20 dB extension of dynamic range. We are also pursuing a subranging ADC design with two PMD front-ends connected with fluxon amplifier and subtractor circuitry that promises a dynamic range extension by 25-30 dB. We report signal-to-noise ratio and spur-free dynamic range measurement results for various ADC chips, and project performance for future improvements.
We have been developing a superconducting second-order sigma-delta analog-to-digital converter with a large bandwidth and a large dynamic range for software radio applications. In a superconducting second-order sigma-delta modulator utilizing a passive integrator and single-flux-quantum (SFQ) feedback, gain to compensate the large attenuation in the passive integrator of the modulator is required to obtain a large dynamic range. In this paper, a second-order modulator utilizing multi-flux-quantum (MFQ) generators creating the needed gain is reported and the design and experimental test results of the elementary circuits including a comparator, a first-order modulator, and the MFQ generator are described. The digital outputs of the comparator and the first-order modulator were experimentally evaluated, where the input dependence of the comparator switching probability and the noise-shaping properties of the modulator were clearly observed. The low speed operation of the MFQ generator creating three SFQ pulses was experimentally confirmed. The other circuits were also tested at low frequencies.
A flash-type superconducting A/D (analog/digital) converter is proposed. The basis low-frequency operation of this converter, which compromises a quantum flux parametron (QFP) and an RF SQUID (superconducting quantum interference device), has been observed. The RF SQUID consists of a Josephson junction and a load inductor which is part of the QFP. It converts an analog signal to period digital signals of one quantum flux (2.07*10/sup -5/ W-b) per cycle. The QFP works as both an amplifier and a comparator of the periodic digital signals, by adding an exciting signal. This A/D converter is expected to achieve high-speed operation of 20 GHz. Several 4-bit A/D converter circuits were fabricated, using the conventional Nb-Pb alloy process, with a junction size of 5 mu m*5 mu m and supercurrent density of 200 A/cm/sup 2/. Basic operation at 100 KHz was confirmed experimentally.>