We have proposed an improved design of the front-end circuit for superconducting analog-to-digital (A/D) converters. The assumed structure of the A/D converter consists of a front-end circuit based on single flux quantum circuitry and a back-end circuit based on semiconductor circuits. To complete the A/D converter, it is necessary to enable synchronous operation between the front-end circuit and assumed back-end circuit. In the present framework, the front-end circuit consists of a ladder-type pulse generator, a modulator, a hybrid DEMUX, shift-registers and stack-type amplifiers. The voltage level of the output data signal is enlarged to about 10 mV by using stack-type amplifiers. Furthermore, the timing margin for synchronization is improved by using a hybrid demultiplexing method. We also have designed a front-end circuit based on the present framework and verified its functionalities at low speed. It was experimentally confirmed that the timing margin in a 1-to-4 hybrid DEMUX was enlarged to three times as large as in the conventional binary-tree DEMUX. A high-voltage output signal of 11 mV was also obtained. From these results, we conclude that functionalities of the designed front-end circuit are correct.
We have proposed an improved design of the front-end circuit for superconducting analog-to-digital (A/D) converters. The assumed structure of the A/D converter consists of a front-end circuit based on single flux quantum circuitry and a back-end circuit based on semiconductor circuits. To complete the A/D converter, it is necessary to enable synchronous operation between the front-end circuit and assumed back-end circuit. In the present framework, the front-end circuit consists of a ladder-type pulse generator, a modulator, a hybrid DEMUX, shift-registers and stack-type amplifiers. The voltage level of the output data signal is enlarged to about 10 mV by using stack-type amplifiers. Furthermore, the timing margin for synchronization is improved by using a hybrid demultiplexing method. We also have designed a front-end circuit based on the present framework and verified its functionalities at low speed. It was experimentally confirmed that the timing margin in a 1-to-4 hybrid DEMUX was enlarged to three times as large as in the conventional binary-tree DEMUX. A high-voltage output signal of 11 mV was also obtained. From these results, we conclude that functionalities of the designed front-end circuit are correct.
We designed a front-end circuit for an analog-to-digital (A/D) converter based on single flux quantum circuitry and tested its functionality at a frequency of up to 43 GHz. The front-end circuit consisted of a pulse generator, a sigma-delta modulator, a 1-to-8 demultiplexer (DEMUX), and superconducting quantum interference device (SQUID) amplifiers. There were 2518 Josephson junctions in the front-end circuit. To operate the circuit at high speed, we designed robust timing against variations in circuit parameters. By using circuit simulations based on the Monte Carlo method, we estimated spread in time lag between clock and data pulses. From this estimate, the timing was optimized to operate the circuit at 40 GHz. The demonstration of the front-end circuit was carried out using the on-chip testing method. Output data were acquired from the modulator through DEMUX. We confirmed proper sigma-delta modulation by analyzing the dependence of the density "1" in the output data on input current level. The proper operation was confirmed in a range of 37-43 GHz. Furthermore, the amplification by the SQUID amplifier was also confirmed at low speed. These results indicate the complete operation of the front-end circuit for superconductive A/D converter.
Interface circuits are the key components that enable the hybrid integration of superconductor and semiconductor digital electronics. The design requirements of superconductor-semiconductor interface circuits vary depending on the application, such as high-performance classical computing, superconducting quantum computing, and digital signal processing. In this survey, various interface circuits are categorized based on the working principle and structure. The superconducting output drivers are explored, which are capable of converting and amplifying, e.g., single flux quantum (SFQ) voltage pulses, to voltage levels that semiconductor circuits can process. Several trade-offs between circuit- and system-level design parameters are examined. Accordingly, parameters such as the data rate, output voltage, power dissipation, layout area, thermal/heat load of cryogenic cables, and bit-error rate are considered.
Superconductor electronics for high-performance computing and high-speed analog-to-digital converters requires multi-channel digital data links. Most difficult is the amplification of the weak signals from the superconductor circuit to the volt level of semiconductor electronics. We developed a hybrid digital interface based on a Josephson latching driver, the so-called Suzuki stack, and a clocked CMOS comparator. The input can be directly triggered by a single flux quantum pulse and the output provides a 1 V CMOS-level signal. In contrast to existing systems, our interface is optimized for ultra-low-power consumption to enable its application for parallel multi-bit data interfaces. We provide evaluation of various types of Suzuki stacks and various CMOS comparators. We present experimental data on the delay of the overall hybrid interface and the total power consumption. The bit-error rate has been measured to be below 10-12. We will discuss the trade-off among circuit robustness, speed, and power consumption.
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
We describe the design of a new oversampled analog-to-digital converter (ADC) based on phase modulation-demodulation (PMD) architecture. In a PMD ADC, the analog input signal modulates the phase of a periodic stream of fluxons applied to a modulator circuit for subsequent demodulation in a clocked synchronizer circuit to produce a digital code. The new modulator provides a way to quadruple the average fluxon transport rate, and hence the input dynamic range, by replacing the single junction interferometer with a high-speed symmetric divide-by-4 circuit. The divider acts as a 1:4 asynchronous demultiplexer which distributes incoming fluxons among its four quarter-rate outputs. This four-fold rate reduction, at the modulator output, allows one to increase the ADC maximum input slew rate to 2 fluxons per clock period, achieving 2 additional bits of resolution at the same sampling clock frequency. We have designed and fabricated a quarter-rate ADC front-end and present low frequency test results for the same. The ADC comprises a quarter-rate quantizer which has been successfully tested at an input frequency of 81.92 GHz.
Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. We report recent advances in the low-pass phase-modulation-demodulation (PMD) oversampled analog-to-digital converter (ADC). The oversampled data from the PMD front-end are passed along with sampling clock to an on-chip digital filter. In the past, the maximum frequency of operation of such chips were limited by that of the digital decimation filter (DDF) to about 30 GHz. Recently, we have designed a chip that allows the PMD front-end to be clocked twice as fast as the DDF, resulting in sampling rates of 46.08 GHz and 29.44 GHz for chips with critical current densities of 4.5 and 1 kA/cm2respectively. We have also designed a new PMD front-end, with a quarter-rate quantizer (QRQ) that allows 18-20 dB extension of dynamic range. We are also pursuing a subranging ADC design with two PMD front-ends connected with fluxon amplifier and subtractor circuitry that promises a dynamic range extension by 25-30 dB. We report signal-to-noise ratio and spur-free dynamic range measurement results for various ADC chips, and project performance for future improvements.