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IEICE Transactions on Electronics

High-Resolution Analog-to-Digital Converters toward Software-Defined-Radio Receivers

Akira Fujimaki

Published Feb 1, 2006• 4 citations
Publisher

Abstract

We describe three types of software-defined-radio (SDR) receivers based on superconducting technologies. The superconducting analog bandpass filters are essential for all types of the receivers. Another key component is an analog-to-digital converters (ADCs), which are required to have high resolution with a broad band width. The complementary A ADC based on the single-flux-quantum circuit is a promising candidate for the SDR receivers because it has a practical nature together with above-mentioned requirements. The experimentally obtained signal-to-noise ratio (SNR) and sensitivity, which are closely related to the resolution, are 34 dB and 20 μA for a quarter of the full-scale input with a band width of about 20 MHz. If we use the optimum decimation filter, the ADC is expected to have the SNR of 82 dB and the sensitivity of 300 nA. These values meet the requirements of the easiest type of the SDR receiver. After new fabrication process has been introduced and the architecture of the ADC has been improved, all types of recievers could be realized based on suoerconductors.

DOI
10.1093/ietele/e89-c.2.113

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Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE•Jun 23, 1994•1 citation
We describe three types of software-defined-radio (SDR) receivers based on superconducting technologies. The superconducting analog bandpass filters are essential for all types of the receivers. Another key component is an analog-to-digital converters (ADCs), which are required to have high resolution with a broad band width. The complementary A ADC based on the single-flux-quantum circuit is a promising candidate for the SDR receivers because it has a practical nature together with above-mentioned requirements. The experimentally obtained signal-to-noise ratio (SNR) and sensitivity, which are closely related to the resolution, are 34 dB and 20 μA for a quarter of the full-scale input with a band width of about 20 MHz. If we use the optimum decimation filter, the ADC is expected to have the SNR of 82 dB and the sensitivity of 300 nA. These values meet the requirements of the easiest type of the SDR receiver. After new fabrication process has been introduced and the architecture of the ADC has been improved, all types of recievers could be realized based on suoerconductors.
We have studied software-defined radios (SDRs) based on superconducting devices. The increasing data rate in mobile communications will require a band-width of up to a few hundred MHz in the future. We have confirmed numerically the broad-band characteristic of oversampled analog-to-digital converters including a lowpass and bandpass modulator. Furthermore, the bandpass modulator constructed without a resistor is found to have sensitivity improved by two orders of magnitude compared to that of the lowpass modulator. This result means that the digital RF radio architecture based on a bandpass ADC is better suited for a future SDR receiver.
Software-Defined Radio (SDR), as explained in [1], is a promising concept for the wireless communication industry since the entire transceiver function can be implemented in software, avoiding the replacement of hardware each time the system has to be upgraded. However, the practical implementation of such a system is depended on the hardware, which consists of precise, ultra highspeed electronic devices such as Analog-to-Digital Converters (ADCs). The present state-of-the-art semiconductor ADCs cannot be used for the implementation of SDR in the near future [2]. Some of the factors that hamper the implementation are the requirements of very high speed of a few tens of GHz and the high resolution (e.g. 16 bits) at these speeds. On the other hand, using the Low-Temperature Superconducting (LTS) technology [3], which relays on the quantum mechanical property of superconductors, very high-speed electronic devices with the accuracy of a flux quantum, can be constructed. In a closed superconducting loop, the magnetic flux can exist only in discrete quantized amounts equal to the multiples of the magnetic flux quantum, φ0 = h/2e ~ 2.07x10 Wb. The theoretical speed limit of such a Rapid Single Flux Quantum (RSFQ) device is close to 1 THz [4]. These RSFQ circuits are the fastest of all devices built in any known technology. The basic building block of an RSFQ circuit is the Josephson Junction (JJ), which is formed when two superconductors are separated by an interface. Since RSFQ circuits work at extremely high speeds, testing and verification of such a device is a difficult and challenging task. Direct testing at these speeds is not possible at this moment. Furthermore, the costs of the equipment required for such tests would be extremely high. Hence methods have to be developed to reduce the requirements of external
We present results of a preliminary analysis of possible front-ends of a software defined radio base station receiver containing superconductor Rapid Single-Flux-Quantum (RSFQ) components. The main component of such a front-end, an oversampling analog-to-digital converter (ADC) with expected internal clock rate up to 20 GHz has already been developed and fabricated with commercially available 3.5-/spl mu/m, 1-kA/cm/sup 2/ niobium-trilayer technology. Simulations show that, even with such crude feature size, the superconductor ADC components can outperform their semiconductor counterparts.
Last year we presented the first fully operational superconducting Analog-to-Digital Converter (ADC) with on-chip Digital Signal Processing (DSP). Here we review this device and introduce completed and prospective innovations required to exceed the performance of the best semiconductor counterparts. The ADC chip contains 2 basic parts: a "fundamental" ADC operating at about 20 GHz sampling rate and a digital decimation filter which attenuates high-frequency noise components and reduces the sampling rate to match it with the bandwidth of an input signal. Our short term goal is to achieve 14 bits Spurious Free Dynamic Range (SFDR) for 60 MHz signal bandwidth by using the standard 1000 A/cm/sup 2/ Nb-trilayer fabrication technology commercially available at HYPRES, Inc.
A wide variety of applications, ranging from radio-frequency (RF) receivers for broadband communications and signal detection, on earth and in space, would benefit from high-performance superconductor analog-to-digital converters (ADCs), based on magnetic flux quantization and fast switching Josephson junctions. Superconductor ADCs are capable of very high sample rates (100 GHz or more), very high linearity, and high sensitivity. Nyquist-rate ADCs use the high sample rate to digitize a wide instantaneous bandwidth (tens of GHz) and are useful for wideband spectrum monitoring as well as high-end scientific instrumentation. Delta and delta-sigma oversampling ADCs use the high linearity to achieve programmable trade-off between dynamic range and instantaneous bandwidth. These lowpass and bandpass ADCs have been used for direct digitization of narrower (tens to hundreds of MHz) RF bands in the 1-20 GHz range for a variety of communications, intelligence, electronic warfare, and radar applications. Another application area of these cryogenic ADCs is for outputs of cryogenic sensor arrays and terahertz mixers. Recent advances in various classes of ADCs for different applications are described.
We have developed a new architecture for a superconducting high-resolution analog-to-digital converter (ADC) which is highly beneficial for IR array readout applications due to its high sensitivity, wide dynamic range and sub-mW power consumption. This ADC is based on the principles of magnetic flux quantization, direct differential coding and decimation filtering. The digital part of the ADC employs elements of the Rapid Single Flux Quantum logic family which are capable of clock frequencies in excess of 100 GHz. We discuss the limits of ADC performance and present an analysis of the power consumption in these ADCs. We also report experimental verification of several key components of this architecture in Niobium technology (operating at 4.2 K), particularly the implementation of a synchronizer unit (necessary for the generation of the differential digital code) as well as a dual-counter synchronous ADC.