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Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

Multigigahertz performance of a superconducting analog-to-digital converter

Howard Cam Luong, T. Van Duzer

Published Jul 2, 1994• 0 citations
Publisher

Abstract

This paper presents the progress we have made on our design, fabrication, and testing of a fully parallel superconducting analog-to-digital converter (ADC) with multi-GHz clock frequencies and input bandwidth. To our best knowledge, this converter is the first flash-type analog-to-digital converter ever reported in Josephson technology that fully integrates a quantizer and a thermometer-to-binary encoder to achieve binary outputs. In this design, the quantizer consists of 2(superscript N-1 comparators, each of which is realized using a hysteretic one- junction sampling SQUID driving a two-junction readout SQUID. A new logic family has been designed based on the same comparator building block and has been used to implement the thermometer-to- binary encoder. Taking advantage of the fact that the encoder's input is thermometer-coded, we have designed three-input and four-input quasi-XOR gates with only three NAND gates and therefore reduced significantly the total gate count. Functionalities of all the sub-circuits have been verified experimentally at clock frequencies up to 3 GHz, which is limited by our currently available testing equipment.

DOI
10.1117/12.181009

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This paper presents the progress we have made on our design, fabrication, and testing of a fully parallel superconducting analog-to-digital converter (ADC) with multi-GHz clock frequencies and input bandwidth. To our best knowledge, this converter is the first flash-type analog-to-digital converter ever reported in Josephson technology that fully integrates a quantizer and a thermometer-to-binary encoder to achieve binary outputs. In this design, the quantizer consists of 2(superscript N-1 comparators, each of which is realized using a hysteretic one- junction sampling SQUID driving a two-junction readout SQUID. A new logic family has been designed based on the same comparator building block and has been used to implement the thermometer-to- binary encoder. Taking advantage of the fact that the encoder's input is thermometer-coded, we have designed three-input and four-input quasi-XOR gates with only three NAND gates and therefore reduced significantly the total gate count. Functionalities of all the sub-circuits have been verified experimentally at clock frequencies up to 3 GHz, which is limited by our currently available testing equipment.
This work addresses new signal processing circuits using the special features of superconductivity. A novel flash-type analog-to-digital converter based on a comparator invented in the preceding contract period was demonstrated. The comparator was shown to be useful as a logic gate and an encoder was designed with it. A high-resolution delta-sigma analog-to-digital converter was devised with superconductive components in spite of the lack of an analog integrator in this technology. Positive theoretical results are being followed up experimentally. A simple flux-shuttle single-flux-quantum shift register was devised and several different readout schemes were studied. A six- bit-long version was successfully tested at 1 GHz. A decoder that takes in a five-bit word to select one of 32 output lines was completed. The design involved very tight limitations on current and power. The decoder was combined with a serial-to-parallel converter and operated at 2 GHz. A study of the appropriate architectures for various types of superconductive or Josephson digital technology was developed: an inductance-extraction program.
The authors report on the high-speed operation of a superconducting comparator circuit, based on coupling the quantum flux parametron (QFP) to an RF SQUID, which can be used to build a flash-type analog-to-digital converter (ADC). Simulations of this circuit show that it is expected to achieve operation with input signal bandwidths greater than 4 GHz and with a dynamic range equal to at least 4 b of resolution. A QFP-based comparator fabricated with a process using NbN/Pb-alloy Josephson junctions of 5 mu m by 5 mu m and a current density of 100 A/cm/sup 2/ has been examined to evaluate the properties of the QFP-ADC. Analog-to-digital conversion of the comparator has been observed with a QFP activation frequency up to 18.2 GHz. By employing a sampling method, input signals with frequencies up to 5.4 GHz have also been digitized.>
We have designed a fully integrated 5-bit flash-type single-flux quantum (SFQ) analog-to-digital converter (ADC), in which an error correction and a bit-interleaving circuit are integrated with complementary quasi-one-junction SQUID (CQOS) comparators, and we verified its operation in experiments. Two types of look-back error correction circuits with different clock schemes were designed for the integrated ADCs to avoid the gray zone in comparators and to convert gray code to binary code. The interleaving circuit was also used in the ADC to add one extra bit. A binary 5-bit A/D converter was integrated into an IC chip. Then, input waveforms at low frequencies were successfully retrieved from the binary data of the A/D converter without any errors. We also confirmed that the A/D converter operated properly by conducting tests in our cryocooling system using a 4K-GM cryocooler after the chip was flip-chip bonded onto a multi-chip-module (MCM) carrier. We also used the beat frequency method to test and confirm that the CQOS comparator operated effectively at high frequency, i.e., 3 bits at 15 GHz in the binary code operation and 4 bits at 15 GHz in the gray code operation. Furthermore, operations at sampling frequencies of up to 32 and 50 GHz with a low-frequency analog input signal were experimentally confirmed for a 4-bit comparator circuit with a critical current density Jcof 2.5 kA/cm2and 10 kA/cm2, respectively.
Successful utilization of the quasi one-junction SQUID (QOS) as a signal comparator for analog-to-digital conversion (ADC) has been demonstrated by several groups, This idea is extended to show how similar comparators can be integrated into an all rapid single flux quantum (RSFQ) digital architecture. Comparators are interrogated by SFQ sampling pulses and in turn give output according to the RSFQ convention. One- and two-bit ADC's have been simulated, fabricated and tested at low speed. Total performance of these devices is estimated within the framework of a multiple bit parallel flash ADC architecture.>
The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra energy efficient data conversion architectures that remain functional at deep cryogenic temperatures.In this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a novel quantum enhanced Josephson junction field effect transistor (JJFET).Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current controlled superconducting devices while aligning naturally with CMOS style design methodologies.Building on our previously developed Verilog A compact model calibrated to experimental data, we design and simulate a three bit JJFET based flash ADC.The core comparator block is realized through careful bias current selection and augmented with a three terminal nanocryotron to precisely define reference voltages.Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic level restoration across stages.Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage driven superconducting mixed signal circuits.This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum classical co-processors, low-power AI accelerators, and next generation energy constrained computing platforms.
The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. In this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.