The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra energy efficient data conversion architectures that remain functional at deep cryogenic temperatures.In this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a novel quantum enhanced Josephson junction field effect transistor (JJFET).Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current controlled superconducting devices while aligning naturally with CMOS style design methodologies.Building on our previously developed Verilog A compact model calibrated to experimental data, we design and simulate a three bit JJFET based flash ADC.The core comparator block is realized through careful bias current selection and augmented with a three terminal nanocryotron to precisely define reference voltages.Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic level restoration across stages.Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage driven superconducting mixed signal circuits.This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum classical co-processors, low-power AI accelerators, and next generation energy constrained computing platforms.
The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra energy efficient data conversion architectures that remain functional at deep cryogenic temperatures.In this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a novel quantum enhanced Josephson junction field effect transistor (JJFET).Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current controlled superconducting devices while aligning naturally with CMOS style design methodologies.Building on our previously developed Verilog A compact model calibrated to experimental data, we design and simulate a three bit JJFET based flash ADC.The core comparator block is realized through careful bias current selection and augmented with a three terminal nanocryotron to precisely define reference voltages.Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic level restoration across stages.Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage driven superconducting mixed signal circuits.This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum classical co-processors, low-power AI accelerators, and next generation energy constrained computing platforms.
The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. In this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.
The growing demand for ultra low power computing and the emergence of quantum technologies have intensified interest in cryogenic electronics, particularly superconducting devices. Despite their promise, current controlled superconducting components face fundamental challenges in cascadability, limiting their effectiveness in complex logic architectures. To overcome this, recent efforts have focused on developing gate tunable superconducting devices, such as Josephson junction field effect transistors (JJFETs). However, achieving robust control and sufficient supercurrent gain, both critical for transistor-like performance in logic circuits remains a key challenge. A recent advancement in JJFET design, based on InAs and GaSb heterostructures, demonstrates enhanced gain and favorable device characteristics suitable for circuit integration. Building on this innovation, we propose and analyze fundamental voltage controlled logic topologies using the quantum enhanced JJFET. We develop a Verilog A based circuit compatible compact model of the quantum enhanced JJFET which accurately captures the experimentally observed device characteristics. To ensure cascadability, our logic circuits incorporate the multilayered Heater Nanocryotron (nTron), a superconducting nanowire-based thermal switch. Through simulation based analysis, we demonstrate the successful implementation of fundamental logic gates, including NOT, NAND, and NOR. Furthermore, we design a 3 input majority gate, which plays a pivotal role in quantum and reversible computing due to its universality. Finally, to demonstrate the cascadability of our proposed logic topology, we demonstrate the operation of a 2 input XOR gate based on our designed JJFET based NOT, NAND, and NOR gate.
Cryogenic (cryo) memory blocks are envisioned to be crucial components for - (i) scalable quantum computing systems with> 1000 qubits [1], and (ii) superconducting (SC) single flux quantum (SFQ) systems [2]. Decades of research has led to a whole host of cryo-memory variants (SC, non-SC, and hybrid), and more are being actively explored. Despite having such massive interest in the search for cryo-storage solutions, the design possibilities for compatible sense amplifiers (SA) remain largely unexplored. The existing approaches for cryogenic sensing are mostly agnostic to the unique properties of the memory array [3]–[5]. For example, the recently proposed SC and twistronic memories promise seamless compatibility with the cryogenic processors in terms of speed, power, and temperature range [4]–[7]. However, they rely on current-driven read operation, and necessitate voltage-based sensing. Therefore, a current-based cryo-SA [3] cannot be used for these emerging cryo-memory variants. In this work, we propose a voltage sense amplifier (VSA) for cryogenic memories utilizing the Josephson junction field effect transistor (JJFET) [8] as the primary component, and the heater cryotron (hTron) [4], [9] as an auxiliary entity. We exploit their coupled interactions to sense ultra-low (< 1 mV) voltage difference (customary for many cryo-memory technologies [4]–[7]) between the binary memory states (0/1) at/below 4 Kelvin temperature.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
This paper presents the progress we have made on our design, fabrication, and testing of a fully parallel superconducting analog-to-digital converter (ADC) with multi-GHz clock frequencies and input bandwidth. To our best knowledge, this converter is the first flash-type analog-to-digital converter ever reported in Josephson technology that fully integrates a quantizer and a thermometer-to-binary encoder to achieve binary outputs. In this design, the quantizer consists of 2(superscript N-1 comparators, each of which is realized using a hysteretic one- junction sampling SQUID driving a two-junction readout SQUID. A new logic family has been designed based on the same comparator building block and has been used to implement the thermometer-to- binary encoder. Taking advantage of the fact that the encoder's input is thermometer-coded, we have designed three-input and four-input quasi-XOR gates with only three NAND gates and therefore reduced significantly the total gate count. Functionalities of all the sub-circuits have been verified experimentally at clock frequencies up to 3 GHz, which is limited by our currently available testing equipment.
A systematic research on the development of cryogenic complementary metal-oxide semiconductor (cryo-CMOS) circuits, for implementing the required control electronics to manipulate the quantum bit (qubit) state, is performed over the last few years. Scalability constitutes a key term regarding the evolution of quantum computing from theory to practical application and CMOS technology has been proven to be a promising candidate for implementing the coveted scalable next-generation quantum computers (QCs). Mixed-signal blocks, used for uniting the analog and digital domains, play a key role in the efficient functionality of the qubit control/readout system, thus there is an ever-increasing interest in their high-performance circuit realization. The critical challenge in this venture is to achieve efficient cryogenic operation at low temperatures, i.e., close to the qubit around 4 K, simultaneously keeping power requirements at low values. An overview and comparison of the cryo-CMOS Digital-to-Analog converter (DAC) and Analog-to-Digital converter (ADC) circuit implementations for quantum computing applications that heretofore have been proposed in the literature is presented in this work. A discussion on the challenges and future strategic steps that are henceforth required to proceed toward the development of a functional scalable quantum computer is also conducted.