Due to power consumption and speed limitations, the development of CMOS-based large-scale integrated circuits has stagnated in the post-Moore era. While superconducting digital integrated circuit is a promising solution due to its low power consumption and latency. However, the lack of large-scale cryogenic storage units prevents most superconducting chips from being deployed in practical applications. To fully utilize the advantages of superconducting chips and successfully apply them in processing large datasets, we propose a novel heterogeneous processor based on CMOS-based circuits and superconducting chips for processing pattern-matching tasks. In our proposed architecture, a novel communication architecture that enables high-speed, reliable communication between 12 GHz superconducting chips and CMOS circuits is proposed. The hardware overhead for high-speed communication in superconducting chips can be minimized by this approach. In addition, the data communication rate of a single channel can reach 12 Gbps. Simultaneously, we present a 12 GHz, large-scale superconducting chip with 6286 Josephson Junctions that can perform 16-bit pattern matching using the SIMIT-Nb03 process. We have successfully applied our proposed heterogeneous processor to the gene sequence alignment. The processor that uses only one superconducting chip has a throughput of 1.5 Gbp/s (billion base pairs per second), whereas a processor with two superconducting chips has 3 Gbp/s.
Due to power consumption and speed limitations, the development of CMOS-based large-scale integrated circuits has stagnated in the post-Moore era. While superconducting digital integrated circuit is a promising solution due to its low power consumption and latency. However, the lack of large-scale cryogenic storage units prevents most superconducting chips from being deployed in practical applications. To fully utilize the advantages of superconducting chips and successfully apply them in processing large datasets, we propose a novel heterogeneous processor based on CMOS-based circuits and superconducting chips for processing pattern-matching tasks. In our proposed architecture, a novel communication architecture that enables high-speed, reliable communication between 12 GHz superconducting chips and CMOS circuits is proposed. The hardware overhead for high-speed communication in superconducting chips can be minimized by this approach. In addition, the data communication rate of a single channel can reach 12 Gbps. Simultaneously, we present a 12 GHz, large-scale superconducting chip with 6286 Josephson Junctions that can perform 16-bit pattern matching using the SIMIT-Nb03 process. We have successfully applied our proposed heterogeneous processor to the gene sequence alignment. The processor that uses only one superconducting chip has a throughput of 1.5 Gbp/s (billion base pairs per second), whereas a processor with two superconducting chips has 3 Gbp/s.
A superconductive ring-pipelined network system is proposed to improve performance of multi-processor systems, and a prototype chip is designed. A throughput of a data exchange between processor elements limits the effective performance of the multi-processor systems. The features of the superconductive ring-pipelined network system are a high-clock-frequency operation by using high-speed Josephson gates and wide band superconductive transmission lines, and a high-density package because of its low power consumption. These advantages significantly reduce pipeline loss and improve flexibility in data exchange. Therefore, this network system is capable of improving the overall effective performance of multiprocessor systems. The prototype chip consists of three Josephson ring interface circuits and superconductive interconnections positioned in between these interface circuits. There are a total 1,130 gates. The prototype chip is designed to be operated up to a clock frequency of 10 GHz. Therefore, the total system throughput is estimated to be 60 Gbps.>
As the demand for energy efficiency rises, researchers are increasingly prioritizing the quest for energy-efficient chip design. Superconducting SFQ circuit technology has garnered attention due to its ultra-high speed and low power consumption characteristics. In this paper, we propose a layout method called Maximum Operating Frequency Constraint (MOFC) for SFQ circuit design. Using this method, we demonstrated a 32-bit bit-parallel string-matching processor fabricated based on SIMIT-Nb03P technology, which holds practical value. The MOFC method focuses on achieving high bit-width processor design within constrained area cost in SFQ circuits, contributing to less energy consumption. To the best of our knowledge, this represents the first demonstrated instance of a superconducting SFQ chip achieving successful internal 32-bit data parallel processing. Our chip has been fabricated and tested, revealing not only its capability for 32-bit bit-parallel processing at a high speed of 12 GHz but also its achievement of an energy efficiency ratio of up to 251 GOPS/W.
A 1-GHz-clock Josephson microcomputer system was developed to demonstrate the possibility of a high-speed superconducting computer system. It consists of a 4-b data processor chip and a 1-kb RAM chip. For the fabrication of these Josephson integrated circuits, a cross-shaped Nb-AlO/sub x/-Nb Josephson junction process was developed in order to realize small junction size and improve critical current uniformity, and has made fabrication of LSIs with several thousand gates possible. A latchup-free DC flip-flop is an important element in the high-speed Josephson logic and memory circuits, having been applied to an all-DC-powered Josephson RAM with asynchronous access capability. A low-inductance chip-to-chip carrier is an architectural and design concept for the Josephson computer's 1-GHz-clock operation, suppressing the crosstalk between the AC power and the output signals. Each chip is 7 mm square and is fabricated using a 2.5- mu m-rule Nb-AlO/sub x/-Nb junction process. The chips are connected on a superconducting carrier by solder bumps in a die size of 15 mm by 25 mm. The system is constructed from 8123 Josephson interferometer devices and is operable in a 1-ns cycle with 50-mW power dissipation.
A critical component for high bandwidth communications links is a digital switch. Desirable features of a digital switch include: high input/output bandwidth, high channel count, scalability, low latency and interchannel skew. Superconductive circuits, with simultaneous high speed and low power advantages (even including the requisite cryocooler) have been applied to a highly scaleable crossbar switch, useful in supercomputer networks, massively parallel processing (MPP), and high data rate telecommunications. We report here on the testing of a 16/spl times/16 switch chip based on the switch chip component of the highly scaleable crossbar system. We have successfully transmitted multi-Gb/s data through this superconducting switch, with packet destination addressing decoded from the header of the data packet. The data are transmitted to a separate superconducting amplifier chip, mounted on a superconducting multi-chip module with the switch. The switch is a crossbar architecture, voltage state design, and operated to beyond 3 Gb/s. The amplifier is a clocked latching stack of Josephson junctions. Output of the amplifier at 6.2 Gb/s is 7.0 mV, which facilitates the interface of the module to its users. BER of the two-chip assembly is 10/sup -9/ or less above 2 Gb/s.
This paper describes our programme to develop and demonstrate ultra-high performance single flux quantum (SFQ) VLSI technology that will enable superconducting digital processors for petaFLOPS-scale computing. In the hybrid technology, multi-threaded architecture, the computational engine to power a petaFLOPS machine at affordable power will consist of 4096 SFQ multi-chip processors, with 50 to 100 GHz clock frequency and associated cryogenic RAM. We present the superconducting technology requirements, progress to date and our plan to meet these requirements. We improved SFQ Nb VLSI by two generations, to a 8 kA cm −2 , 1.25 µm junction process, incorporated new CAD tools into our methodology, demonstrated methods for recycling the bias current and data communication at speeds up to 60 Gb s −1 , both on and between chips through passive transmission lines. FLUX-1 is the most ambitious project implemented in SFQ technology to date, a prototype general-purpose 8 bit microprocessor chip. We are testing the FLUX-1 chip (5K gates, 20 GHz clock) and designing a 32 bit floating-point SFQ multiplier with vector-register memory. We report correct operation of the complete stripline-connected gate library with large bias margins, as well as several larger functional units used in FLUX-1. The next stage will be an SFQ multi-processor machine. Important challenges include further reducing chip supply current and on-chip power dissipation, developing at least 64 kbit, sub-nanosecond cryogenic RAM chips, developing thermally and electrically efficient high data rate cryogenic-to-ambient input/output technology and improving Nb VLSI to increase gate density.
Superconductive electronics offers a unique combination of high bandwidth and low power for mission critical hardware such as digital processors at 20 to 100 GHz, microwatt per bit analog to digital converters, large digital switches at multi-Gb/s data rates, and low noise parametric amplifiers. This cryogenic technology, typically operating at a few degrees or a few tens of degrees Kelvin, depends upon the unique physics of superconducting materials such as Nb, NbN, and YBaCuO, and the fundamental circuit element, the Josephson junction (JJ) to create unique architectures of unprecedented design efficiency and performance. These circuits are based on the single flux quantum (SFQ) logic family, a technology that has no parallel in semiconductor electronics. Digital data is transmitted by voltage pulses with amplitude less than 1 mV, but at extremely high speeds. Individual gates have been operated as high as 370 GHz. In this paper, we present a brief overview of superconductive digital technology, describe some recent circuits, and discuss how the challenges to superconductive technology are being met, including the use of multi-chip module (MCM) technology, and the potential use of III-V HBT and HEMT circuits to provide interface drivers and amplifiers, possibly operated cryogenically.