As the demand for energy efficiency rises, researchers are increasingly prioritizing the quest for energy-efficient chip design. Superconducting SFQ circuit technology has garnered attention due to its ultra-high speed and low power consumption characteristics. In this paper, we propose a layout method called Maximum Operating Frequency Constraint (MOFC) for SFQ circuit design. Using this method, we demonstrated a 32-bit bit-parallel string-matching processor fabricated based on SIMIT-Nb03P technology, which holds practical value. The MOFC method focuses on achieving high bit-width processor design within constrained area cost in SFQ circuits, contributing to less energy consumption. To the best of our knowledge, this represents the first demonstrated instance of a superconducting SFQ chip achieving successful internal 32-bit data parallel processing. Our chip has been fabricated and tested, revealing not only its capability for 32-bit bit-parallel processing at a high speed of 12 GHz but also its achievement of an energy efficiency ratio of up to 251 GOPS/W.
As the demand for energy efficiency rises, researchers are increasingly prioritizing the quest for energy-efficient chip design. Superconducting SFQ circuit technology has garnered attention due to its ultra-high speed and low power consumption characteristics. In this paper, we propose a layout method called Maximum Operating Frequency Constraint (MOFC) for SFQ circuit design. Using this method, we demonstrated a 32-bit bit-parallel string-matching processor fabricated based on SIMIT-Nb03P technology, which holds practical value. The MOFC method focuses on achieving high bit-width processor design within constrained area cost in SFQ circuits, contributing to less energy consumption. To the best of our knowledge, this represents the first demonstrated instance of a superconducting SFQ chip achieving successful internal 32-bit data parallel processing. Our chip has been fabricated and tested, revealing not only its capability for 32-bit bit-parallel processing at a high speed of 12 GHz but also its achievement of an energy efficiency ratio of up to 251 GOPS/W.
A fast Fourier transform (FFT) is an algorithm that computes the discrete Fourier transform (DFT) of a sequence at high speed. FFT can convert a signal from time domain to frequency domain, and is wildly used in digital signal processing field. In this paper, a high-speed, low-power FFT processor is demonstrated up to 47.8GHz with the measured power consumption of 5.3mW, using single-flux quantum (SFQ) logic. This is the first complete FFT processor implementation using superconducting technology, performing 8-point 7-bit FFT in a bit-serial computing manner. The test chip fabricated using a 1.0 μm 9-layer process consists of 17 455 Nb/AlOx/Nb Josephson junctions (JJs), rendering itself the largest superconducting digital circuit capable of iterative data computing. The correct operation of the chip has been experimentally confirmed at a maximum operating frequency of 47.8GHz (word speed 8GHz) by conducting on-chip high-speed testing.
The Collatz conjecture asserts that by a repeated iteration rule, the operation starting from any positive integer n, eventually produces the value of “1.” The main contribution of this paper is to demonstrate a single-flux-quantum (SFQ)-based hardware algorithm that performs an exhaustive search to verify the Collatz conjecture. The circuit consists of a 16-bit integer register, a high-frequency clock generator, and a central processor. This design can perform at up to a maximum clock frequency of 90 GHz with a total power consumption of about 0.85 mW in simulation, based on the AIST 10 kA/cm2advanced Nb process. An LR-biasing approach further reduces the power consumption, whereas the computing speed can be accelerated by a factor of 20 when accelerating approaches are adopted. The assessments show that our design can process 2 × 107numbers every second with an energy efficiency of about 5 × 1010numbers per Joule.
New superconductor single flux quantum logics with no static power dissipation in bias resistors, such as Reciprocal Quantum Logic (RQL), offer opportunities to create energy-efficient superconductor processors operating at high frequencies with ultra-low power consumption. This paper discusses the results of our work on the cell-level design and analysis of a benchmark set of 32-/64-bit RQL processor integer and floating-point units such as adders, multipliers, an arithmetic-logic unit, and an array shifter, as well as small 1-4 Kbit RQL on-chip storage components such as register files, on-chip memory, and the top level caches. Our layout-aware design process includes the complete cell-level design and approximate physical layout of the circuits followed by the VHDL simulation, verification, and energy profiling using our RQL VHDL cell library tuned to the future MIT Lincoln Laboratory 10 kA/cm2 248 nm process with 10 Nb metal layers and the minimum JJ critical current of 38 μA. Our designs have the energy efficiency of ~1.0 single-precision TFLOPS/W and '0.5 double-precision TFLOPS/W for floating-point units, and ~1-24 TOPS/W for 32-bit integer units at room temperature using the cryocooling efficiency of 0.1 % (1000 W/W). The 1-4 Kbit 32-/64-bit multi-ported scratchpad memory, register files, write-through and write-back caches designed with RQL Non-Destructive Read-Out storage cells have the average energy consumption of 3.0-9.5 fJ/bit/operation at room temperature using the cryocooling efficiency of 0.1%. While these results are very promising, more work is needed to evaluate the contribution of the energy costs of instruction scheduling and off-chip main memory access to the energy efficiency of RQL computing across a whole system.
Processors, the essential part of computer systems, have dramatically improved their performance with transistors' shrinking technology since the first processors are developed in the early 1970s.However, around the 2000s, the problem of power consumption became apparent, and it became hard to improve the clock frequency, which significantly contributed to the improvement of performance.Although processors' performance improvement has been maintained by introducing multi-core designs, it will be challenging to improve chip performance only with conventional CMOS computing technology continuously after the end of transistors' scaling.To solve these problems, this dissertation focuses on a cryogenic computing technology using superconductor single flux quantum (SFQ) logic that has both high speed and low power consumption.SFQ logic uses low-voltage impulseshaped signals for logic operations, which allows the ultra-fast (10 -12 s) and lowenergy switching (10 -19 J).Due to these potentials, several researchers have so far contributed to SFQ-related research, and several physical implementations, including processors, have successfully demonstrated at the outstanding frequency, e.g., several tens of GHz.However, this is the performance at the logic gate level in the circuit, and when converted to the processor's performance based on software execution, it remains at the same level as conventional CMOS processors.The fundamental problem existing behind the SFQ processors is the lack of architectural optimizations to exploit the full potential of SFQ devices.Moreover, although several circuits' demonstrations have successfully shown the device-level potential, few studies focus on the architectural unit designs to show the SFQ computing potential.Therefore, the following questions must be clearly addressed to show the SFQ computing's potential: (1) what architecture is promising for this technology, (2) how is the feasibility and effectiveness of the architecture, (3) how to evaluate the effective performance and power efficiency of the target designs.To solve the problem, this dissertation firstly explores the architectural design space of SFQ processors to determine the basic design guidelines for the realization of high-performance SFQ processors.Specifically, we assume a simple processor (i.e., in-order scalar processor) and analyze the effect of two architectural parameters (i.e., instruction pipeline stages and bit-width) on performance and power consumption.As a result, the bit-parallel processing and gate-level deep pipeline structure are suitable for achieving high performance in SFQ processors.Moreover, the result indicates that SFQ processors must conceal almost all pipeline stalls to achieve high performance in such an ultra-deep pipelining.Second, this dissertation designs and implements a 4-bit SFQ processor chip as a prototype to clarify our proposed architectural design guidelines' effectiveness and feasibility.As a result, we confirm the correct operation at 32 GHz of clock frequency with 6.5 mW of power consumption.Moreover, this dissertation has extended into the 64-bit processor based on these results and evaluated its power efficiency with the cooling overhead for keeping SFQ circuits at 4 kelvin.The power efficiency, including the cooling cost, is estimated to at most 7.1 GOPS/W, and our processor outperforms the CMOS processor model 7.8 times.Third, this dissertation proposes and evaluates the SFQ accelerator design for neural network applications to show the real potential of SFQ computing.Specifically, this dissertation designs the basic architecture of the neural network accelerator based on the basic design guidelines for SFQ processors and develops an evaluation environment based on power performance modeling.Besides, we analyze the performance bottleneck and optimize the architecture.As a result of the evaluation, our design outperforms about 23 and 1.2 times higher performance and power efficiency with the cooling cost compared to a state-of-the-art CMOS accelerator, respectively.List of Tables 3.1 Delay parameters . . . . . . . . .
Processors, the essential part of computer systems, have dramatically improved their performance with transistors' shrinking technology since the first processors are developed in the early 1970s.However, around the 2000s, the problem of power consumption became apparent, and it became hard to improve the clock frequency, which significantly contributed to the improvement of performance.Although processors' performance improvement has been maintained by introducing multi-core designs, it will be challenging to improve chip performance only with conventional CMOS computing technology continuously after the end of transistors' scaling.To solve these problems, this dissertation focuses on a cryogenic computing technology using superconductor single flux quantum (SFQ) logic that has both high speed and low power consumption.SFQ logic uses low-voltage impulseshaped signals for logic operations, which allows the ultra-fast (10 -12 s) and lowenergy switching (10 -19 J).Due to these potentials, several researchers have so far contributed to SFQ-related research, and several physical implementations, including processors, have successfully demonstrated at the outstanding frequency, e.g., several tens of GHz.However, this is the performance at the logic gate level in the circuit, and when converted to the processor's performance based on software execution, it remains at the same level as conventional CMOS processors.The fundamental problem existing behind the SFQ processors is the lack of architectural optimizations to exploit the full potential of SFQ devices.Moreover, although several circuits' demonstrations have successfully shown the device-level potential, few studies focus on the architectural unit designs to show the SFQ computing potential.Therefore, the following questions must be clearly addressed to show the SFQ computing's potential: (1) what architecture is promising for this technology, (2) how is the feasibility and effectiveness of the architecture, (3) how to evaluate the effective performance and power efficiency of the target designs.To solve the problem, this dissertation firstly explores the architectural design space of SFQ processors to determine the basic design guidelines for the realization of high-performance SFQ processors.Specifically, we assume a simple processor (i.e., in-order scalar processor) and analyze the effect of two architectural parameters (i.e., instruction pipeline stages and bit-width) on performance and power consumption.As a result, the bit-parallel processing and gate-level deep pipeline structure are suitable for achieving high performance in SFQ processors.Moreover, the result indicates that SFQ processors must conceal almost all pipeline stalls to achieve high performance in such an ultra-deep pipelining.Second, this dissertation designs and implements a 4-bit SFQ processor chip as a prototype to clarify our proposed architectural design guidelines' effectiveness and feasibility.As a result, we confirm the correct operation at 32 GHz of clock frequency with 6.5 mW of power consumption.Moreover, this dissertation has extended into the 64-bit processor based on these results and evaluated its power efficiency with the cooling overhead for keeping SFQ circuits at 4 kelvin.The power efficiency, including the cooling cost, is estimated to at most 7.1 GOPS/W, and our processor outperforms the CMOS processor model 7.8 times.Third, this dissertation proposes and evaluates the SFQ accelerator design for neural network applications to show the real potential of SFQ computing.Specifically, this dissertation designs the basic architecture of the neural network accelerator based on the basic design guidelines for SFQ processors and develops an evaluation environment based on power performance modeling.Besides, we analyze the performance bottleneck and optimize the architecture.As a result of the evaluation, our design outperforms about 23 and 1.2 times higher performance and power efficiency with the cooling cost compared to a state-of-the-art CMOS accelerator, respectively.List of Tables 3.1 Delay parameters . . . . . . . . .
This paper describes our programme to develop and demonstrate ultra-high performance single flux quantum (SFQ) VLSI technology that will enable superconducting digital processors for petaFLOPS-scale computing. In the hybrid technology, multi-threaded architecture, the computational engine to power a petaFLOPS machine at affordable power will consist of 4096 SFQ multi-chip processors, with 50 to 100 GHz clock frequency and associated cryogenic RAM. We present the superconducting technology requirements, progress to date and our plan to meet these requirements. We improved SFQ Nb VLSI by two generations, to a 8 kA cm −2 , 1.25 µm junction process, incorporated new CAD tools into our methodology, demonstrated methods for recycling the bias current and data communication at speeds up to 60 Gb s −1 , both on and between chips through passive transmission lines. FLUX-1 is the most ambitious project implemented in SFQ technology to date, a prototype general-purpose 8 bit microprocessor chip. We are testing the FLUX-1 chip (5K gates, 20 GHz clock) and designing a 32 bit floating-point SFQ multiplier with vector-register memory. We report correct operation of the complete stripline-connected gate library with large bias margins, as well as several larger functional units used in FLUX-1. The next stage will be an SFQ multi-processor machine. Important challenges include further reducing chip supply current and on-chip power dissipation, developing at least 64 kbit, sub-nanosecond cryogenic RAM chips, developing thermally and electrically efficient high data rate cryogenic-to-ambient input/output technology and improving Nb VLSI to increase gate density.