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Conference on Precision Electromagnetic Measurements

Reduction of microwave attenuation in superconducting microstripline using plasma nitridation

S.I. Park, Jinhee Kim, Hyun Kwon Hong, K.-T. Kim

Published Jun 25, 2003• 0 citations
Publisher

Abstract

We have been developed a new fabrication process of Josephson junction series array (JJA) by using reactive ion etching (RIE) and a self-aligning technique. A plasma nitridation process is also employed in improving the microwave transmission characteristics by blocking the O/sub 2/ from diffusing into the Nb ground-plane by depositing SiO/sub 2/ dielectric layer using plasma enhanced chemical vapor deposition (PECVD) at substrate temperature of 300/spl deg/C.

DOI
10.1109/cpem.2002.1034938

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We have been developed a new fabrication process of Josephson junction series array (JJA) by using reactive ion etching (RIE) and a self-aligning technique. A plasma nitridation process is also employed in improving the microwave transmission characteristics by blocking the O/sub 2/ from diffusing into the Nb ground-plane by depositing SiO/sub 2/ dielectric layer using plasma enhanced chemical vapor deposition (PECVD) at substrate temperature of 300/spl deg/C.
A simple and robust process for fabricating low-T/sub c/ Josephson junction integrated circuits has been developed. The process is designed around the Nb/Al/sub 2/O/sub 3/-Al/Nb trilayer, and utilized nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by plasma-enhanced chemical vapor deposition (PECVD). The PECVD equipment yields a high deposition rate at moderate substrate temperatures. No degradation of the junction characteristics due to these depositions is seen. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44*10/sup -4/. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. A variety of simple circuits using this process technology have been fabricated and tested. More complex circuits are currently under development.
Developed a new fabrication process for 10-V Josephson junction series arrays (JJAs). A plasma nitridation process is employed for reducing the microwave attenuation in the Josephson microstripline. Improvements of microwave attenuation are about 2 dB for test arrays of 2000, 3000, and 4000 Josephson junctions in a single stripline. We obtained stable quantized voltage steps up to 12 V at 76.4 and 86.8 GHz with step amplitudes of more than 5 /spl mu/A and stability times of more than 5 min. The circuits used 14 648 junctions arranged in 8 parallel paths.
A simple and robust process for fabricating low-Tc Josephson junction integrated circuits has been developed. The process is designed around the Nb/A1203-Al/Nb trilayer, and utilizes nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by Plasma Enhanced Chemical Vapor Deposition (PECVD). The PECVD equipment that we use yields a high deposition rate at moderate substrate temperatures. We see no degradation of the junction characteristics due to these depositions. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44 x 10-4. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. We have successfully fabricated and tested a variety of simple circuits using this process technology. Much more complex circuits are currently under development (Fig. 1).
A novel method of fabrication, as described in the following, was developed that ensures a good reproducibility of the junction. Namely, poly-Si was deposited over a Si substrate whose surface had been previously thermally oxidized. The poly-Si overlaid surface was then thermally oxidized. The bridge configuration of the junction was microprocessed by means of electron beam lithography. The fabricated configuration served as a mask in depositing the Nb layer on the substrate by means of rf sputtering to conclude the fabrication of a microbridge Josephson junction. The final process of the formation of the variable thickness microbridge configuration was readily carried out by placing another properly shaped mask over the masking bridge or by forming an SiO2 layer over the poly-Si layer. The SiO2 layer was processed by selective plasma etching so that it would act as a mask over the bridge portion. The stabilization of the characteristics of the junction has been achieved due to the passivation which takes place during the heat treatment in atmosphere by forced oxidation of the Nb film surface and to the annealing of the film itself.
Dielectric loss in low-temperature superconducting integrated circuits can cause lower overall efficiency, particularly in the 90 to 220 GHz regime. We present a method to tune the dielectric loss for silicon oxide deposited by plasma-enhanced chemical-vapor deposition at ambient temperatures. Deposition in an environment with a higher silane-to-oxygen ratio produces silicon oxide films with a lower loss-tangent and a slightly higher optical index of refraction, while contributing no appreciable change in film stress. We measured the dielectric loss by fabricating a series of Nb-SiOx-Nb microstrip resonators in the frequency range of 6 to 9 GHz and comparing their temperature dependence to a model of parasitic two-level-system fluctuators. The dielectric loss-tangent of silicon oxide was improved from 6 ×10-3for stoichiometric silicon dioxide to 2 ×10-3for a more silicon-rich silicon oxide. We present details of the fabrication process and measurements of microstrip resonators.
Our Nb/AlO/sub x//Nb planarized process has been upgraded by adding extra dielectric and Nb wiring layers and the installation of an Inductively Coupled Plasma (ICP) etcher. Much higher quartz etch rates as well as reduced residue are achieved with ICP etch. Etch uniformities of both Nb and quartz are also improved significantly. Damage to Nb during the fabrication process has been investigated. We have found that dry etching in SF/sub 6/ plasma has a significant effect on the quality of Nb films under certain conditions with damage coinciding with the presence of in situ deposited Al.