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IEEE Transactions on Applied Superconductivity

Improvements in Silicon Oxide Dielectric Loss for Superconducting Microwave Detector Circuits

Dale Li, J. Gao, Jason E. Austermann, James A. Beall, Daniel Becker, Hsiao-Mei Cho, Anna E. Fox, N. W. Halverson, J. W. Henning, Gene C Hilton, Johannes Hubmayr, K. D. Irwin, Jeff Van Lanen, John P. Nibarger, Michael D. Niemack

Published Jan 24, 2013• 24 citations
Publisher

Abstract

Dielectric loss in low-temperature superconducting integrated circuits can cause lower overall efficiency, particularly in the 90 to 220 GHz regime. We present a method to tune the dielectric loss for silicon oxide deposited by plasma-enhanced chemical-vapor deposition at ambient temperatures. Deposition in an environment with a higher silane-to-oxygen ratio produces silicon oxide films with a lower loss-tangent and a slightly higher optical index of refraction, while contributing no appreciable change in film stress. We measured the dielectric loss by fabricating a series of Nb-SiOx-Nb microstrip resonators in the frequency range of 6 to 9 GHz and comparing their temperature dependence to a model of parasitic two-level-system fluctuators. The dielectric loss-tangent of silicon oxide was improved from 6 ×10-3for stoichiometric silicon dioxide to 2 ×10-3for a more silicon-rich silicon oxide. We present details of the fabrication process and measurements of microstrip resonators.

DOI
10.1109/tasc.2013.2242951

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Dielectric loss in low-temperature superconducting integrated circuits can cause lower overall efficiency, particularly in the 90 to 220 GHz regime. We present a method to tune the dielectric loss for silicon oxide deposited by plasma-enhanced chemical-vapor deposition at ambient temperatures. Deposition in an environment with a higher silane-to-oxygen ratio produces silicon oxide films with a lower loss-tangent and a slightly higher optical index of refraction, while contributing no appreciable change in film stress. We measured the dielectric loss by fabricating a series of Nb-SiOx-Nb microstrip resonators in the frequency range of 6 to 9 GHz and comparing their temperature dependence to a model of parasitic two-level-system fluctuators. The dielectric loss-tangent of silicon oxide was improved from 6 ×10-3for stoichiometric silicon dioxide to 2 ×10-3for a more silicon-rich silicon oxide. We present details of the fabrication process and measurements of microstrip resonators.
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Low-loss deposited dielectrics will benefit superconducting devices such as integrated superconducting spectrometers, superconducting qubits, and kinetic inductance parametric amplifiers. Compared with planar structures, multilayer structures such as microstrips are more compact and eliminate radiation loss at high frequencies. Multilayer structures are most easily fabricated with deposited dielectrics, which typically exhibit higher dielectric loss than crystalline dielectrics. We measure the subkelvin and low-power microwave and millimeter-submillimeter-wave dielectric loss of hydrogenated amorphous silicon carbide (aaa-SiC:H), using superconducting chips with Nb-Ti-N/a\mathrm{N}/aN/a-SiC:H/Nb-Ti-N microstrip resonators. We deposit the aaa-SiC:H by plasma-enhanced chemical vapor deposition at a substrate temperature of $400{\phantom{\rule{0.1em}{0ex}}}^{\ensuremath{\circ}}\mathrm{C}$. The aaa-SiC:H has a millimeter-submillimeter loss tangent ranging from $0.9\ifmmode\times\else\texttimes\fi{}{10}^{\ensuremath{-}4}$ at 270 GHz to $1.5\ifmmode\times\else\texttimes\fi{}{10}^{\ensuremath{-}4}$ at 385 GHz. The microwave loss tangent is $3.1\ifmmode\times\else\texttimes\fi{}{10}^{\ensuremath{-}5}$. These are the lowest low-power subkelvin loss tangents that have been reported for microstrip resonators at millimeter-submillimeter and microwave frequencies. The aaa-SiC:H films are free of blisters and have low stress: $\ensuremath{-}20$ MPa compressive at 200-nm thickness to 60 MPa tensile at 1000-nm thickness.
We present a lab-on-chip experiment to accurately measure losses of superconducting microstrip lines at microwave and sub-mm wavelengths. The microstrips are fabricated from NbTiN, which is deposited using reactive magnetron sputtering, and amorphous silicon which is deposited using plasma-enhanced chemical vapor deposition (PECVD). Sub-mm wave losses are measured using on-chip Fabry-P{é}rot resonators (FPR) operating around $350\ $GHz. Microwave losses are measured using shunted half-wave resonators with an identical geometry and fabricated on the same chip. We measure a loss tangent of the amorphous silicon at single-photon energies of tan⁡δ=3.7±0.5×10−5\tanδ=3.7\pm0.5\times10^{-5}tanδ=3.7±0.5×10−5 at $6\ $GHz and tan⁡δ=2.1±0.1×10−4\tanδ= 2.1\pm 0.1\times10^{-4}tanδ=2.1±0.1×10−4 at $350\ $GHz. These results represent very low losses for deposited dielectrics, but the sub-mm wave losses are significantly higher than the microwave losses, which cannot be understood using the standard two-level system loss model.
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Silicon-on-insulator technology is widely used to fabricate silicon based devices, from advanced transistors to photonic circuits or nanomechanical systems. Integrating low loss superconducting quantum circuits with silicon-on-insulator substrates enables to couple the advantages offered by the mature silicon technology to the exquisite sensitivity of superconducting circuits. The natural approach, inherited from research in superconducting microwave devices, is to use a substrate made with highly resistive silicon, known for its low level of microwave losses. In this work, using superconducting microwave resonators, we show that counterintuitively, standard resistivity silicon-on-insulator substrates perform better than high resistivity silicon-on-insulator substrates at cryogenic temperatures. In the latter case, the presence of a parasitic sheet conduction at the interface between bulk silicon and silicon oxide acts as the dominant loss mechanism. This parasitic sheet can be suppressed using substrates with intentionally induced traps. In such substrates, losses are ultimately limited by the dielectric losses of the silicon oxide layer. These substrates offer interesting perspectives for the development of superconducting nanoelectromechanical systems. First, the release, i.e. the removal of the silicon oxide, could be limited to the moving parts, thereby maintaining the mechanical integrity of the rest of the device. Additionally, such structure would enhance heat evacuation into the bulk of the substrate which is an issue in current devices such as microwave-to-optics converters.
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