Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Applied Superconductivity

A novel Josephson adder without carry propagation delay

F. Li, Michitada Morisue

Published Mar 1, 1993• 10 citations
Publisher

Abstract

The authors describe a novel Josephson adder based on the radix-2 signed-digit number representation. In the proposed adder, the addition operation can be carried out in a constant time independent of word length owing to the elimination of the carry propagation chain. A critical path for generating the sum signal can be completed through only three series gates. A carry signal and an intermediate sum signal for all digits in the adder are simultaneously generated in the first step, and the final sum signal is obtained in the second step. Features of the proposed adder are a simple construction, ultra-high speed, and low power consumption. The principle of constructing the adder with an 8 b word length using superconducting quantum interference devices (SQUIDs) is described in detail, and simulation results are presented. Results show that reliable operation can be achieved for the longest delay time of 120 ps for the 8 b adder.>

DOI
10.1109/77.233979

Related papers

A novel Josephson ternary multiplier

Michitada Morisue, Jun Endo, T. Morooka +2 more

A novel Josephson ternary logic circuit to perform multiplication is proposed. The fundamental circuit of the multiplier is based on Josephson complementary ternary logic circuit (JCTL). In this paper the principle of the ternary multiplier is described. We have fabricated the multiplier using SQUIDs which were made of Nb/AlOx/Al/Nb junctions, and measurements of the logic operation of the circuit were carried out. The results showed satisfactory operation of the multiplier, which agreed well with the results of simulation. The advantages of the proposed ternary multiplier are capability of ultra-high speed computation, low power consumption and very simple construction with less number of elements to perform a ternary multiplication.

IEEE Transactions on Applied Superconductivity•Jun 1, 1997•2 citations

Carry time of magnetically coupled Josephson adder circuits

Hajime Yamada, Yoshichika Ichimiya, Akira Ishida

Abstract A carry circuit for Josephson adder has been studied and tested experimentally. For carry calculation, a ripple carry process by asymmetrical interferometric majority gates is employed because it can reduce the gate number‐add time products compared with carry look ahead process by conventional OR‐AND gates. Add time measurement has been performed with these carry circuits connected to dummy sum circuits. Operation speed as fast as 740 ps was obtained for 16‐bit calculation, which shows excellent agreement with computer simulation. By the analysis, it has been clarified that the operation speed is limited by impedance mismatched input lines.

Electronics and Communications in Japan (Part I Communications)•Jan 1, 1984•1 citation

Design of fast digit-serial adders using SFQ logic circuits

Park Heejoung, Yuki Yamanashi, Nobuyuki Yoshikawa +2 more

We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digit-serial adder using the SRL 2.5kA/cm2 niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of ± 15% at 25GHz. Its maximum operation frequency was 30GHz.

IEICE Electronics Express•Jan 1, 2009•4 citations

A compact realization of an n-bit quantum carry skip adder circuit with optimal delay

Nusrat Jahan Lisa, Hafiz Md. Hasan Babu

This paper presents the design of a novel n-bit carry skip adder by its core components using quantum logic. The novelty of the proposed adder is that it considers a new design with optimal delay. Moreover, it is the first time in quantum circuit synthesis that the quantum realization of a carry skip adder is shown in terms of quantum gates, power and area, etc. Our proposed quantum multiplexer gate (QMG) and quantum comparison gate (QCG) perfectly operates as a 2-to-1 MUX and a comparison circuit, respectively. Using QMG and QCG as a unit element of construction, we optimize the design of Carry Skip Adder. A generalized architecture of the proposed n-bit adder has also been presented. The comparative study shows that the proposed quantum carry skip adder performs better than the existing carry skip adders with the increasing number of bits; e.g., the proposed 128-bit carry skip adder improves 40.96% on number of quantum gates, 48.19% on delay, 22.22% on garbage outputs and 40.96% on area and power over the existing best one. In addition, we also simulate the proposed adder using Microwind DSCH 3.5 and QuIDDPro software to show the correctness of the circuit.

NASA/ESA Conference on Adaptive Hardware and Systems (AHS)•Jul 1, 2014•2 citations

Design and fabrication of an adder circuit in the extended phase-mode logic

Takeshi Onomi, Takashi Yamashita, Yoshinao Mizugaki +1 more

We present the design and the fabrication of an adder circuit in the extended phase-mode logic family. The phase-mode logic is a single flux quantum (SFQ) logic which utilizes an SFQ as an information bit carrier. The single-bit adder circuit is made up of an INHIBIT gate which is the basic device of the phase-mode logic. The circuit has been designed and fabricated using Nb/AlO/sub x//Nb Josephson junctions with Josephson critical current density of 1.0 kA/cm/sup 2/. In order to confirm the circuit operation, the fabricated adder circuit has been tested at low speed. For investigating the possibility of a high-frequency operation, dc voltages generated by fluxon pulse trains have been measured. From the Josephson voltage-frequency relation, the result shows that the circuit has potential to complete the carry operation within 20 psec.

IEEE Transactions on Applied Superconductivity•Jun 1, 1997•3 citations

A parallel full adder circuit using Josephson junctions

S. Hasuo, Hideo Suzuki, Kouichi Dazai

Detailed investigations have been carried out on a Josephson parallel full adder as an example of a functional circuit using Josephson junctions. This circuit can be constructed with fewer devices as compared with conventional Josephson adders. Two-junction interferometers (d.c.-SQUIDs) are utilized as switching elements of the circuit. Only (2N+1) d.c.-SQUIDs are required for construction of an N bit circuit. Discussions focus on design theory of the full adder circuit. An experimental 4 bit circuit operation is also demonstrated.

IEEE Journal of Solid-State Circuits•Feb 1, 1981•3 citations
The authors describe a novel Josephson adder based on the radix-2 signed-digit number representation. In the proposed adder, the addition operation can be carried out in a constant time independent of word length owing to the elimination of the carry propagation chain. A critical path for generating the sum signal can be completed through only three series gates. A carry signal and an intermediate sum signal for all digits in the adder are simultaneously generated in the first step, and the final sum signal is obtained in the second step. Features of the proposed adder are a simple construction, ultra-high speed, and low power consumption. The principle of constructing the adder with an 8 b word length using superconducting quantum interference devices (SQUIDs) is described in detail, and simulation results are presented. Results show that reliable operation can be achieved for the longest delay time of 120 ps for the 8 b adder.>
A novel Josephson ternary logic circuit to perform multiplication is proposed. The fundamental circuit of the multiplier is based on Josephson complementary ternary logic circuit (JCTL). In this paper the principle of the ternary multiplier is described. We have fabricated the multiplier using SQUIDs which were made of Nb/AlOx/Al/Nb junctions, and measurements of the logic operation of the circuit were carried out. The results showed satisfactory operation of the multiplier, which agreed well with the results of simulation. The advantages of the proposed ternary multiplier are capability of ultra-high speed computation, low power consumption and very simple construction with less number of elements to perform a ternary multiplication.
Abstract A carry circuit for Josephson adder has been studied and tested experimentally. For carry calculation, a ripple carry process by asymmetrical interferometric majority gates is employed because it can reduce the gate number‐add time products compared with carry look ahead process by conventional OR‐AND gates. Add time measurement has been performed with these carry circuits connected to dummy sum circuits. Operation speed as fast as 740 ps was obtained for 16‐bit calculation, which shows excellent agreement with computer simulation. By the analysis, it has been clarified that the operation speed is limited by impedance mismatched input lines.
We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digit-serial adder using the SRL 2.5kA/cm2 niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of ± 15% at 25GHz. Its maximum operation frequency was 30GHz.
This paper presents the design of a novel n-bit carry skip adder by its core components using quantum logic. The novelty of the proposed adder is that it considers a new design with optimal delay. Moreover, it is the first time in quantum circuit synthesis that the quantum realization of a carry skip adder is shown in terms of quantum gates, power and area, etc. Our proposed quantum multiplexer gate (QMG) and quantum comparison gate (QCG) perfectly operates as a 2-to-1 MUX and a comparison circuit, respectively. Using QMG and QCG as a unit element of construction, we optimize the design of Carry Skip Adder. A generalized architecture of the proposed n-bit adder has also been presented. The comparative study shows that the proposed quantum carry skip adder performs better than the existing carry skip adders with the increasing number of bits; e.g., the proposed 128-bit carry skip adder improves 40.96% on number of quantum gates, 48.19% on delay, 22.22% on garbage outputs and 40.96% on area and power over the existing best one. In addition, we also simulate the proposed adder using Microwind DSCH 3.5 and QuIDDPro software to show the correctness of the circuit.
We present the design and the fabrication of an adder circuit in the extended phase-mode logic family. The phase-mode logic is a single flux quantum (SFQ) logic which utilizes an SFQ as an information bit carrier. The single-bit adder circuit is made up of an INHIBIT gate which is the basic device of the phase-mode logic. The circuit has been designed and fabricated using Nb/AlO/sub x//Nb Josephson junctions with Josephson critical current density of 1.0 kA/cm/sup 2/. In order to confirm the circuit operation, the fabricated adder circuit has been tested at low speed. For investigating the possibility of a high-frequency operation, dc voltages generated by fluxon pulse trains have been measured. From the Josephson voltage-frequency relation, the result shows that the circuit has potential to complete the carry operation within 20 psec.
Detailed investigations have been carried out on a Josephson parallel full adder as an example of a functional circuit using Josephson junctions. This circuit can be constructed with fewer devices as compared with conventional Josephson adders. Two-junction interferometers (d.c.-SQUIDs) are utilized as switching elements of the circuit. Only (2N+1) d.c.-SQUIDs are required for construction of an N bit circuit. Discussions focus on design theory of the full adder circuit. An experimental 4 bit circuit operation is also demonstrated.