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Design of fast digit-serial adders using SFQ logic circuits

Park Heejoung, Yuki Yamanashi, Nobuyuki Yoshikawa, Masamitsu Tanaka, Akira Fujimaki

Published Jan 1, 2009• 4 citations
Publisher

Abstract

We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digit-serial adder using the SRL 2.5kA/cm2 niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of ± 15% at 25GHz. Its maximum operation frequency was 30GHz.

DOI
10.1587/elex.6.1408

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