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IEEE International Superconductive Electronics Conference (ISEC)

Demonstration of an 8-Bit SFQ Carry Look-Ahead Adder Using Clockless Logic Cells

Takahiro Kawaguchi, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi

Published Jul 1, 2015• 15 citations
Publisher

Abstract

We have designed, fabricated and experimentally demonstrated an 8-bit carry look-ahead adder using clockless AND and NIMPLY cells. A clockless cell is a logic cell without a clock input. Comprared to the circuit using only clocked cells, the circuit using clockless cells has fewer routing wires and splitters. Decrease of the numbers of wires and splitters can reduce the area of a circuit. The 8-bit adder core (without SFQ-to-DC and DC-to-SFQ converters, the clock generator and input and output shift registers for the high frequency test) has 3320 Josephson junctions (JJs) occupying the area of 1.84 mm2. It is designed for the target operation frequency is 10 GHz with 3 pipeline stages, and the delay from the clock input to the primary outputs of 74 ps at most at the bias voltage of 2.5 mV. The adder chip was fabricated using AIST 10-kA/cm2 Advanced Process (ADP2) and tested at low and high frequency with measured bias margins of +16%/+6%. The measured maximum frequency was 12.87 GHz.

DOI
10.1109/isec.2015.7383439

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We have designed, fabricated and experimentally demonstrated an 8-bit carry look-ahead adder using clockless AND and NIMPLY cells. A clockless cell is a logic cell without a clock input. Comprared to the circuit using only clocked cells, the circuit using clockless cells has fewer routing wires and splitters. Decrease of the numbers of wires and splitters can reduce the area of a circuit. The 8-bit adder core (without SFQ-to-DC and DC-to-SFQ converters, the clock generator and input and output shift registers for the high frequency test) has 3320 Josephson junctions (JJs) occupying the area of 1.84 mm2. It is designed for the target operation frequency is 10 GHz with 3 pipeline stages, and the delay from the clock input to the primary outputs of 74 ps at most at the bias voltage of 2.5 mV. The adder chip was fabricated using AIST 10-kA/cm2 Advanced Process (ADP2) and tested at low and high frequency with measured bias margins of +16%/+6%. The measured maximum frequency was 12.87 GHz.
An architecture of rapid single-flux-quantum logic circuits using clockless gates is proposed. Compared with a circuit composed of only clocked gates, a circuit using clockless gates includes fewer clocked gates, and therefore, a smaller clock distribution network. A circuit in the proposed architecture is constructed from pipeline stages. Each pipeline stage consists of a column of clocked gates and a succeeding block of clockless gates. The function of a pipeline register of a stage is implemented by the latching function of the clocked gates in the column. The combinational logic of a stage is implemented by the logic function of the clocked gates in the column and that of the clockless gates in the block. We designed a two-stage-pipelined 4-bit carry-lookahead-adder using clockless gates as a design example of the proposed architecture. It had reductions of the count of clocked gates and the area by 33 and 13%, respectively, compared with that composed of only clocked gates. The 4-bit adder in the proposed architecture was fabricated and demonstrated with the maximum clock frequency of 21.4 GHz and the bias margin of ±16%.
A single flux quantum (SFQ) logic cell library has been developed for the 10kA/cm2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5kA/cm2 to 10kA/cm2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100GHz.
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100-GHz Single-Flux-Quantum Bit-Serial Adder Based on 10-kA/cm2{\rm kA/cm}^{2}kA/cm2 Niobium Process
This paper reports the design and test results of a single-flux-quantum (SFQ) bit-serial adder, which we designed with a target-clock frequency of 100 GHz, to investigate several techniques for producing ultra-high-speed computations using SFQ circuits. The bit-serial adder was designed based on a new cell library developed for the ISTEC Advanced Process, where the critical current density and McCumber-Stewart parameters of Josephson junctions were increased to 10 kA/cm2and 2.0, respectively, to obtain higher operating frequencies. In addition, we adopted a circuit-design technique based on state transitions excluding a feedback loop in a typical bit-serial adder, and redesigned the NOR gate with the McCumber-Stewart parameter increased to 4.0 to improve performance. As a result, we experimentally obtained a sufficient dc bias margin of ±18% from low frequencies to 60 GHz, and verified the correctness of operations up to 93 GHz. We also demonstrated that the introduction of a higher bias voltage or large inductors in series with bias resistors is effective for achieving faster operation.
Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. In this paper, we conducted the high-frequency operation and energy measurement of an AQFP circuit with more than 1000 Josephson junctions in the experiment. We designed an 8-bit carry look-ahead adder (CLA) using AQFP gates and fabricated it using an advanced fabrication technology, the AIST 10 kA/cm2 Nb high-speed standard process. The correct operation of the 8-bit CLA was demonstrated at a 1-GHz clock frequency for a critical carry propagation test vector. The energy dissipation of the 8-bit CLA was measured by observing the power of excitation current. Our results showed that the energy dissipation per operation of the 8-bit CLA can be estimated to be approximately 1.5 aJ, or 24kBT per junction, where kB is the Boltzmann constant and T is the operating temperature.