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Superconductor Science and Technology

Design and implementation of a high-speed bit-serial SFQ adder based on the binary decision diagram

Kenji Kawasaki, K. Yoda, Nobuyuki Yoshikawa, Akira Fujimaki, Hirotaka Terai, Shinichi Yorozu

Published Nov 7, 2003• 1 citation
Publisher

Abstract

We have designed a high-speed SFQ bit-serial carry-save adder based on the binary decision diagram (BDD). A simple bit-serial carry-save adder based on the BDD we first designed has a carry-feedback loop. Its input data frequency is limited by the propagation delay in the feedback loop. In our second adder design, we have replaced one BDD gate with a nondestructive binary switch, by which we can eliminate the carry-feedback loop. We have designed the high-speed BDD SFQ bit-serial adder using the NEC 2.5 kA cm −2 Nb standard process and the CONNECT cell library. The circuit simulation indicates that the maximum operating frequency is 38 GHz and the dc bias margin at 10 GHz is ±23%. We have confirmed its correct operation in the on-chip high-speed test. The maximum operating frequency was found to be 23.8 GHz.

DOI
10.1088/0953-2048/16/12/039

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