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Applied Superconductivity

Single flux quantum one-decimal-digit RNS adder

Nada Vukovic, M. J. Feldman

Published Oct 1, 1999• 1 citation
Publisher

Abstract

Residue number system (RNS) arithmetic has a promising role for fault-tolerant high throughput superconducting single flux quantum (SFQ) circuits for digital signal processing (DSP) applications. We have designed one of the basic computational blocks used in DSP circuits, one-decimal-digit RNS adder. A new design for its main component, the single-modulus adder, has been developed. It combines simple and robust RSFQ elementary cells, both combinational and sequential. The central units are a circular shift register, a code converter, and the clock control circuitry. Our mod5 adder employs 195 Josephson junctions, consumes 50 μW of power, and occupies an area of less than 2 mm2. Chips were fabricated at HYPRES, Inc. using 1 kA/cm2 low-Tc Niobium technology. The mod5 adder was successfully tested at low speed, and gave experimental bias margins of ±26%.

DOI
10.1016/s0964-1807(99)00018-6

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Residue number system (RNS) arithmetic has a promising role for fault-tolerant high throughput superconducting single flux quantum (SFQ) circuits for digital signal processing (DSP) applications. We have designed one of the basic computational blocks used in DSP circuits, one-decimal-digit RNS adder. A new design for its main component, the single-modulus adder, has been developed. It combines simple and robust RSFQ elementary cells, both combinational and sequential. The central units are a circular shift register, a code converter, and the clock control circuitry. Our mod5 adder employs 195 Josephson junctions, consumes 50 μW of power, and occupies an area of less than 2 mm2. Chips were fabricated at HYPRES, Inc. using 1 kA/cm2 low-Tc Niobium technology. The mod5 adder was successfully tested at low speed, and gave experimental bias margins of ±26%.
Superconducting single flux quantum (SFQ) circuits are promising for digital signal processing systems. However, conventional binary arithmetic does not take full advantage of the fundamental properties of SFQ circuits. The residue number system (RNS) is intrinsically more compatible with single flux quantum circuits, and provides the advantage of modularity, parallelism, carry-free structure, simple multiplication and fault tolerance. We designed a one-decimal-digit adder to demonstrate this new technology. The exclusive use of simple and robust Josephson shift registers creates large margins, simple circuit architecture and high throughput. These attributes are important for state-of-the-art superconducting technology, and are especially crucial for high temperature superconducting digital circuits. We designed, simulated and extensively optimized a mod 5 adder and its subcells. We laid out the circuits and had them fabricated. We tested the low speed functionality of these circuits using a manual test setup and a LabVIEW automated test setup. All the subcell experimental results show decent operation margins and good consistency with the simulation results, and demonstration of the entire mod 5 adder should be straightforward. An SFQ RNS 8-bit multiplier is proposed. Comparing to superconducting binary bit-serial and bit-parallel 8-bit multipliers, it shows an advantage in design simplicity, operation margins, error rate and throughput, along with its unique feature of simple fault tolerance. We thus believe that RNS, rather than binary, could be the natural language for superconducting digital electronics, especially in the application of digital signal processors.
We have designed and developed superconducting single flux quantum (SFQ) digital signal processing circuits using the residue number system (RNS). RNS arithmetic is a complete alternative to binary arithmetic for performing digital computations, which appears to have many advantages for SFQ circuits. We present a scheme for performing all RNS arithmetic functions using Josephson shift registers alone, and suggest that this Is advantageous for high-temperature superconductor computational circuits. We have designed a one-decimal-digit adder, realized with Nb-based superconducting circuitry. Its most complex component, the mod5 adder, has been simulated to show perfect functionality and subcell simulated margins are compared with the experimental results.>
We have designed, fabricated, and tested a rapid single flux quantum (RSFQ) 1 bit arithmetic logic unit (ALU) block. The circuit consists of three DC current driven SFQ switches and a half-adder. We successfully tested the half-adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half-adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached two switches at the input ports of the half-adder to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this set-up, the circuit was successfully tested up to 20 GHz. The chip was fabricated using a standard HYPRES 1 kA cm −2 Nb Josephson junction fabrication process.
We have designed a Rapid Single-Flux-Quantum (RSFQ) bit-serial real-time pipeline multiplier for digital signal processing (DSP) applications. A single-bit module of this multiplier consists of 96 Josephson junctions and uses a B-flip-flop-based carry-save adder (CSA). For HYPRES' standard 1-kA/cm/sup 2/ Nb process with 3.5 /spl mu/m-diameter Josephson junctions the module occupies all area of 350/spl times/600 /spl mu/m/sup 2/. Simulations show that the circuit should dissipate 28 /spl mu/W of power at 2.6 mV dc supply voltage and operate at frequencies of up to 25 GHz. We have successfully tested all cells of the module and verified correct operation of a simplified version of the module at low frequencies. According to numerical simulations, the speed of the multiplier is limited by the CSA. In order to overcome this bottleneck we have developed a concept of a fast carry-save pipeline adder based on XOR gates which uses an RSFQ-specific algorithm for carry bit calculation.>
We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digit-serial adder using the SRL 2.5kA/cm2 niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of ± 15% at 25GHz. Its maximum operation frequency was 30GHz.
We have developed a novel, so-called "push-forward" design approach in Rapid Single-Flux-Quantum (RSFQ) logic. This approach leads to a more efficient circuit design at the gate level using fewer Josephson junctions combined with reasonable circuit parameter margins. Other advantages include higher operational speed and smaller power dissipation. This novel method is based on a specific type of interaction (pushing forward) between single flux quanta already stored by RSFQ gates and newly arriving data SFQ pulses. It implies a reuse of an internal gate memory as well as realization of multi-quantum storage. Using this push-forward design approach, we have designed, optimized, fabricated, and successfully tested two versions of Carry-Save Serial Adders for digital signal processing applications.>