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Superconducting single flux quantum circuits using the residue number system

Qing Ke

Published Oct 3, 1996• 5 citations
OpenAlex

Abstract

Superconducting single flux quantum (SFQ) circuits are promising for digital signal processing systems. However, conventional binary arithmetic does not take full advantage of the fundamental properties of SFQ circuits. The residue number system (RNS) is intrinsically more compatible with single flux quantum circuits, and provides the advantage of modularity, parallelism, carry-free structure, simple multiplication and fault tolerance. We designed a one-decimal-digit adder to demonstrate this new technology. The exclusive use of simple and robust Josephson shift registers creates large margins, simple circuit architecture and high throughput. These attributes are important for state-of-the-art superconducting technology, and are especially crucial for high temperature superconducting digital circuits. We designed, simulated and extensively optimized a mod 5 adder and its subcells. We laid out the circuits and had them fabricated. We tested the low speed functionality of these circuits using a manual test setup and a LabVIEW automated test setup. All the subcell experimental results show decent operation margins and good consistency with the simulation results, and demonstration of the entire mod 5 adder should be straightforward. An SFQ RNS 8-bit multiplier is proposed. Comparing to superconducting binary bit-serial and bit-parallel 8-bit multipliers, it shows an advantage in design simplicity, operation margins, error rate and throughput, along with its unique feature of simple fault tolerance. We thus believe that RNS, rather than binary, could be the natural language for superconducting digital electronics, especially in the application of digital signal processors.

Related papers

Single flux quantum circuits using the residue number system

Qing Ke, M. J. Feldman

We have designed and developed superconducting single flux quantum (SFQ) digital signal processing circuits using the residue number system (RNS). RNS arithmetic is a complete alternative to binary arithmetic for performing digital computations, which appears to have many advantages for SFQ circuits. We present a scheme for performing all RNS arithmetic functions using Josephson shift registers alone, and suggest that this Is advantageous for high-temperature superconductor computational circuits. We have designed a one-decimal-digit adder, realized with Nb-based superconducting circuitry. Its most complex component, the mod5 adder, has been simulated to show perfect functionality and subcell simulated margins are compared with the experimental results.>

IEEE Transactions on Applied Superconductivity•Jun 1, 1995•11 citations

Single flux quantum one-decimal-digit RNS adder

Nada Vukovic, M. J. Feldman

Residue number system (RNS) arithmetic has a promising role for fault-tolerant high throughput superconducting single flux quantum (SFQ) circuits for digital signal processing (DSP) applications. We have designed one of the basic computational blocks used in DSP circuits, one-decimal-digit RNS adder. A new design for its main component, the single-modulus adder, has been developed. It combines simple and robust RSFQ elementary cells, both combinational and sequential. The central units are a circular shift register, a code converter, and the clock control circuitry. Our mod5 adder employs 195 Josephson junctions, consumes 50 μW of power, and occupies an area of less than 2 mm2. Chips were fabricated at HYPRES, Inc. using 1 kA/cm2 low-Tc Niobium technology. The mod5 adder was successfully tested at low speed, and gave experimental bias margins of ±26%.

Applied Superconductivity•Oct 1, 1999•1 citation

Design of fast digit-serial adders using SFQ logic circuits

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We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digit-serial adder using the SRL 2.5kA/cm2 niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of ± 15% at 25GHz. Its maximum operation frequency was 30GHz.

IEICE Electronics Express•Jan 1, 2009•4 citations

Superconductive single-flux quantum technology

Oleg A. Mukhanov

Key digital circuits for signal processing with tens of gigahertz speed and a few microwatts power dissipation have been recently demonstrated using a simple, 2 /spl mu/m linewidth process. These are the fastest digital circuits reported to date. These circuits use novel rapid single flux quantum (RSFQ) technology that takes advantage of the fundamental properties of superconductivity. In this technology, data and clock are picosecond-long quantized voltage pulses corresponding to the transfer of single magnetic flux quanta, /spl Phisub 0/=h/2e=2 mVps. These SFQ pulses are regenerated at each gate and are processed by circuits comprised of overdamped Josephson junctions interconnected via microstrip inductances. The inherent internal memory of all RSFQ gates (primarily flip-flops), combined with high switching speed, makes serial, bit-pipelined circuit design advantageous. This paper presents experiments in RSFQ digital circuits, including an N/spl times/8b serial multiplier, and on-chip test systems based on RSFQ shift registers and on SFQ samplers. They enable test and study of RSFQ circuits at full GHz speed while communicating with semiconductor electronics at low speed.>

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Prospect of Superconductive Digital Circuits Based on Single Flux Quantum Logic.

Akira Fujimaki

I describe the fundamental technologies concerning the single flux quantum (SFQ) logic circuits. Recent remarkable progress in the computer-aided-design (CAD) tool, which is based on the cell-based design technique, enables us to make SFQ integrated circuits. Although the circuit demonstrated so far has 2, 300 Josephson junctions at most, this number will increase because the CAD tool is advancing. The on-chip test system has also been developed to test the high-speed nature of the SFQ circuit. For example, the shift-register employed as a circuit under test operates correctly at 55GHz. I also describe the potential applications of the SFQ circuits. An analog-to-digital converter utilizing the high-speed nature and high sensitivity in the SFQ circuits will be applicable to the front end of the future base stations, which require broad band width, high sensitivity, and flexibility. Packet switches used in the future high-end router need high throughput and functionality. Only SFQ-based packet switches can meet these requirements. Another potential application is a high-end server. We have studied micro-architectures of a processor executing the Java Byte Codes directly and a multiprocessor system constructed by connecting the processors and memories via the ultra-broad-band SFQ network switches. Throughout the study, we employ the concept of the complexity-reduction (CORE), in which the high-speed nature of the SFQ circuits is used for the reduction of the circuit scale or simplification of the micro-architecture; the multiprocessor system has high performances. These clear applications promote rapid technological progress in the SFQ technology, though we must make every endeavor to find new application fields.

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Small-area and high-precision deterministic stochastic adder using single flux quantum circuit

Zeyu Han, Yuya Mandai, Nobuyuki Yoshikawa +1 more

Abstract Superconducting single flux quantum (SFQ) circuits can operate at ultrafast speeds, and their superconducting random number generators (SRNGs) produce high-quality stochastic bit sequences at several tens GHz, with an arbitrary probability of outputting ‘1’, making them ideal for stochastic computing. The conventional superconducting stochastic adder uses a multiplexer (MUX) controlled by a random bit sequence generated by the SRNG. However, the SFQ-based MUX occupies a large circuit area, and any deviation in the probability of the control signal directly degrades the accuracy of stochastic addition. To overcome these limitations, we propose a deterministic stochastic adder comprising only an AND gate, an XOR gate, and a toggle flip-flop. Our design outputs one ‘1’ for every two input ‘1’s, achieving stochastic addition without the random control signal. Compared to the MUX-based stochastic adder, the proposed adder reduces the root-mean-square error by a factor of 32 when adding 1024-bit random sequences, reduces circuit area by 49.0%, and Josephson junction count by 28.1%, while supporting operating frequencies of about 120 GHz in simulation. We fabricated the proposed adder with two SRNGs for generating input sequences using a 10 kA cm −2 Nb four-layer superconducting process. High-speed operation was verified up to approximately 35.4 GHz with a constant bias margin by measuring the average voltage at the input and outputs. To the best of our knowledge, this is the first demonstration of ultrafast stochastic arithmetic operations above 30 GHz.

Superconductor Science and Technology•Jan 1, 2026•0 citations
Superconducting single flux quantum (SFQ) circuits are promising for digital signal processing systems. However, conventional binary arithmetic does not take full advantage of the fundamental properties of SFQ circuits. The residue number system (RNS) is intrinsically more compatible with single flux quantum circuits, and provides the advantage of modularity, parallelism, carry-free structure, simple multiplication and fault tolerance.
We designed a one-decimal-digit adder to demonstrate this new technology. The exclusive use of simple and robust Josephson shift registers creates large margins, simple circuit architecture and high throughput. These attributes are important for state-of-the-art superconducting technology, and are especially crucial for high temperature superconducting digital circuits. We designed, simulated and extensively optimized a mod 5 adder and its subcells. We laid out the circuits and had them fabricated. We tested the low speed functionality of these circuits using a manual test setup and a LabVIEW automated test setup. All the subcell experimental results show decent operation margins and good consistency with the simulation results, and demonstration of the entire mod 5 adder should be straightforward.
An SFQ RNS 8-bit multiplier is proposed. Comparing to superconducting binary bit-serial and bit-parallel 8-bit multipliers, it shows an advantage in design simplicity, operation margins, error rate and throughput, along with its unique feature of simple fault tolerance.
We thus believe that RNS, rather than binary, could be the natural language for superconducting digital electronics, especially in the application of digital signal processors.
We have designed and developed superconducting single flux quantum (SFQ) digital signal processing circuits using the residue number system (RNS). RNS arithmetic is a complete alternative to binary arithmetic for performing digital computations, which appears to have many advantages for SFQ circuits. We present a scheme for performing all RNS arithmetic functions using Josephson shift registers alone, and suggest that this Is advantageous for high-temperature superconductor computational circuits. We have designed a one-decimal-digit adder, realized with Nb-based superconducting circuitry. Its most complex component, the mod5 adder, has been simulated to show perfect functionality and subcell simulated margins are compared with the experimental results.>
Residue number system (RNS) arithmetic has a promising role for fault-tolerant high throughput superconducting single flux quantum (SFQ) circuits for digital signal processing (DSP) applications. We have designed one of the basic computational blocks used in DSP circuits, one-decimal-digit RNS adder. A new design for its main component, the single-modulus adder, has been developed. It combines simple and robust RSFQ elementary cells, both combinational and sequential. The central units are a circular shift register, a code converter, and the clock control circuitry. Our mod5 adder employs 195 Josephson junctions, consumes 50 μW of power, and occupies an area of less than 2 mm2. Chips were fabricated at HYPRES, Inc. using 1 kA/cm2 low-Tc Niobium technology. The mod5 adder was successfully tested at low speed, and gave experimental bias margins of ±26%.
We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digit-serial adder using the SRL 2.5kA/cm2 niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of ± 15% at 25GHz. Its maximum operation frequency was 30GHz.
Key digital circuits for signal processing with tens of gigahertz speed and a few microwatts power dissipation have been recently demonstrated using a simple, 2 /spl mu/m linewidth process. These are the fastest digital circuits reported to date. These circuits use novel rapid single flux quantum (RSFQ) technology that takes advantage of the fundamental properties of superconductivity. In this technology, data and clock are picosecond-long quantized voltage pulses corresponding to the transfer of single magnetic flux quanta, /spl Phisub 0/=h/2e=2 mVps. These SFQ pulses are regenerated at each gate and are processed by circuits comprised of overdamped Josephson junctions interconnected via microstrip inductances. The inherent internal memory of all RSFQ gates (primarily flip-flops), combined with high switching speed, makes serial, bit-pipelined circuit design advantageous. This paper presents experiments in RSFQ digital circuits, including an N/spl times/8b serial multiplier, and on-chip test systems based on RSFQ shift registers and on SFQ samplers. They enable test and study of RSFQ circuits at full GHz speed while communicating with semiconductor electronics at low speed.>
I describe the fundamental technologies concerning the single flux quantum (SFQ) logic circuits. Recent remarkable progress in the computer-aided-design (CAD) tool, which is based on the cell-based design technique, enables us to make SFQ integrated circuits. Although the circuit demonstrated so far has 2, 300 Josephson junctions at most, this number will increase because the CAD tool is advancing. The on-chip test system has also been developed to test the high-speed nature of the SFQ circuit. For example, the shift-register employed as a circuit under test operates correctly at 55GHz. I also describe the potential applications of the SFQ circuits. An analog-to-digital converter utilizing the high-speed nature and high sensitivity in the SFQ circuits will be applicable to the front end of the future base stations, which require broad band width, high sensitivity, and flexibility. Packet switches used in the future high-end router need high throughput and functionality. Only SFQ-based packet switches can meet these requirements. Another potential application is a high-end server. We have studied micro-architectures of a processor executing the Java Byte Codes directly and a multiprocessor system constructed by connecting the processors and memories via the ultra-broad-band SFQ network switches. Throughout the study, we employ the concept of the complexity-reduction (CORE), in which the high-speed nature of the SFQ circuits is used for the reduction of the circuit scale or simplification of the micro-architecture; the multiprocessor system has high performances. These clear applications promote rapid technological progress in the SFQ technology, though we must make every endeavor to find new application fields.
Abstract Superconducting single flux quantum (SFQ) circuits can operate at ultrafast speeds, and their superconducting random number generators (SRNGs) produce high-quality stochastic bit sequences at several tens GHz, with an arbitrary probability of outputting ‘1’, making them ideal for stochastic computing. The conventional superconducting stochastic adder uses a multiplexer (MUX) controlled by a random bit sequence generated by the SRNG. However, the SFQ-based MUX occupies a large circuit area, and any deviation in the probability of the control signal directly degrades the accuracy of stochastic addition. To overcome these limitations, we propose a deterministic stochastic adder comprising only an AND gate, an XOR gate, and a toggle flip-flop. Our design outputs one ‘1’ for every two input ‘1’s, achieving stochastic addition without the random control signal. Compared to the MUX-based stochastic adder, the proposed adder reduces the root-mean-square error by a factor of 32 when adding 1024-bit random sequences, reduces circuit area by 49.0%, and Josephson junction count by 28.1%, while supporting operating frequencies of about 120 GHz in simulation. We fabricated the proposed adder with two SRNGs for generating input sequences using a 10 kA cm −2 Nb four-layer superconducting process. High-speed operation was verified up to approximately 35.4 GHz with a constant bias margin by measuring the average voltage at the input and outputs. To the best of our knowledge, this is the first demonstration of ultrafast stochastic arithmetic operations above 30 GHz.