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International Journal of Power Electronics and Drive Systems/International Journal of Electrical and Computer Engineering

The use of reversible logic gates in the design of residue number systems

A. Asadpour, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi

Published Dec 11, 2022• 0 citations
Publisher

Abstract

Reversible computing is an emerging technique to achieve ultra-low-power circuits. Reversible arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions and multiplications without carry propagation between residue digits. The parallelism and fault-tolerance features of RNS can be leveraged to achieve high-performance reversible computing. This paper proposed RNS full reversible circuits, including forward converters, modular adders and multipliers, and reverse converters used for a class of RNS moduli sets with the composite form {2k, 2p-1}. Modulo 2n-1, 2n, and 2n+1 adders and multipliers were designed using reversible gates. Besides, reversible forward and reverse converters for the 3-moduli set {2n-1, 2n+k, 2n+1} have been designed. The proposed RNS-based reversible computing approach has been applied for consecutive multiplications with an improvement of above 15% in quantum cost after the twelfth iteration, and above 27% in quantum depth after the ninth iteration. The findings show that the use of the proposed RNS-based reversible computing in convolution results in a significant improvement in quantum depth in comparison to conventional methods based on weighted binary adders and multipliers.

DOI
10.11591/ijece.v13i2.pp2009-2022

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Reversible computing is an emerging technique to achieve ultra-low-power circuits. Reversible arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions and multiplications without carry propagation between residue digits. The parallelism and fault-tolerance features of RNS can be leveraged to achieve high-performance reversible computing. This paper proposed RNS full reversible circuits, including forward converters, modular adders and multipliers, and reverse converters used for a class of RNS moduli sets with the composite form {2k, 2p-1}. Modulo 2n-1, 2n, and 2n+1 adders and multipliers were designed using reversible gates. Besides, reversible forward and reverse converters for the 3-moduli set {2n-1, 2n+k, 2n+1} have been designed. The proposed RNS-based reversible computing approach has been applied for consecutive multiplications with an improvement of above 15% in quantum cost after the twelfth iteration, and above 27% in quantum depth after the ninth iteration. The findings show that the use of the proposed RNS-based reversible computing in convolution results in a significant improvement in quantum depth in comparison to conventional methods based on weighted binary adders and multipliers.
Multiplication of quantum states is a frequently used function or subroutine in quantum algorithms and applications, making quantum multipliers an essential component of quantum arithmetic. However, quantum multiplier circuits suffer from high Toffoli depth and T gate usage, which ultimately affects their scalability and applicability on quantum computers. To address these issues, we propose utilizing the Residue Number System (RNS) based distributed quantum multiplication, which executes multiple quantum modulo multiplication circuits across quantum computers or jobs with lower Toffoli depth and T gate usage. Towards this end, we propose a design of Quantum Diminished-1 Modulo(2n+1)(2^{\mathrm{n}} + 1)(2n+1)Multiplier, an essential component of RNS based distributed quantum multiplication. We provide estimates of quantum resource usage and compare them with those of an existing non-distributed quantum multiplier for 6 to 16 qubit sized output. Our comparative analysis estimates up to 46.018% lower Toffoli depth, and reduction in T gates of 34.483% to 86.25%.
Quantum arithmetic operations play a vital role in modern quantum computing applications such as cryptography, signal processing, and large-scale scientific computation. However, conventional quantum multiplication architectures often suffer from high computational complexity, increased Toffoli depth, and excessive T gate consumption, which limit their practical implementation on scalable quantum hardware. This paper presents an optimized distributed quantum multiplication framework based on the Residue Number System (RNS) to improve computational efficiency and scalability. The proposed approach divides large multiplication tasks into multiple modular arithmetic operations that are executed independently across distributed quantum processing units. A Quantum Diminished-1 Modulo (2ⁿ+1) multiplier is incorporated as the fundamental computational block to achieve faster modular multiplication with reduced gate complexity. Performance analysis is carried out for quantum outputs ranging from 6 to 16 qubits and compared with traditional quantum multiplication methods. Experimental results demonstrate significant improvements in resource optimization, including reduced Toffoli depth, minimized T gate utilization, and enhanced execution speed. The proposed framework provides a scalable and efficient solution for next-generation distributed quantum arithmetic systems and supports the development of practical large-scale quantum computing architectures.
A key component of quantum algorithms is the efficient multiplication of quantum states; nevertheless, the scalability of traditional quantum multipliers on quantum hardware is frequently limited by high Toffoli depth and excessive T gate utilization. This research introduces a distributed quantum multiplication framework based on the Residue Number System (RNS) that performs numerous quantum modulo multiplication operations across different quantum processors or computational tasks. We present a Quantum Diminished-1 Modulo (2⋅+1) Multiplier inside this framework, which is a crucial element that improves the effectiveness of RNS-based distributed multiplication. For outputs between 6 and 16 qubits, we present a thorough examination of the quantum resource requirements and contrast the suggested method with a traditional non-distributed quantum multiplier. The results underscore the promise of the suggested strategy for scalable and resource-efficient quantum arithmetic, showing reductions of up to 46.02% in Toffoli depth and 34.48% to 86.25% in T gate count.
Quantum Arithmetic faces limitations such as noise and resource constraints in the current Noisy Intermediate Scale Quantum (NISQ) era quantum computers. We propose using Distributed Quantum Computing (DQC) to overcome these limitations by substituting a higher depth quantum addition circuit with Residue Number System (RNS) based quantum modulo adders. The RNS-based distributed quantum addition circuits possess lower depth and are distributed across multiple quantum computers/jobs, resulting in higher noise resilience. We propose the Quantum Superior Modulo Addition based on RNS Tool (QSMART), which can generate RNS sets of quantum adders based on multiple factors such as depth, range, and efficiency. We also propose a novel design of Quantum Diminished-1 Modulo (2n+ 1) Adder (QDMA), which forms a crucial part of RNS-based distributed quantum addition and the QSMART tool. We demonstrate the higher noise resilience of the Residue Number System (RNS) based distributed quantum addition by conducting simulations modeling Quantinuum's HI ion trap-based quantum computer. Our simulations demonstrate that RNS-based distributed quantum addition has 11.36% to 133.15% higher output probability over 6-bit to 10-bit non-distributed quantum full adders, indicating higher noise fidelity. Furthermore, we present a scalable way of achieving distributed quantum addition higher than limited otherwise by the 20-qubit range of Quantinuum HI.
The prediction and forthcoming of a quantum computer into the real-world is the much gained research area over the last decades, which initiated the usefulness and profit of reversible computation because of its potentiality to reduce power consumption in designing arithmetic circuits. In this paper, two design approaches are proposed for the design of a reversible Binary-Coded-Decimal adder. The first approach is implemented and realized from reversible gates proposed by researchers in the technical literature capable of breaking down into primitive quantum gates, whereas the second approach is realized from the existing synthesizable reversible gates only. Parallel implementations of such circuits have been carried out through the proper selection and arrangements of the gates to improve the reversible performance parameters. The proposed design approaches offer a low quantum cost along-with lower delay and hardware complexity for any n-digit addition. Analysis results of proposed design 1 show appreciable improvements over gate count, quantum cost, and delay by at least 9 %, 17 %, and 26 % respectively, whereas, the proposed design 2 show that the results significantly improve the parameters (gate count, quantum cost, and delay) by at least 45 %, 33 %, and 50 % respectively compared to existing counterparts found in the literature.